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Method of forming planar Cu interconnects without chemical mechanical polishing

A technology of electropolishing and copper interconnection structure, which is applied in the direction of semiconductor devices, electrical components, circuits, etc.

Inactive Publication Date: 2006-12-27
INT BUSINESS MASCH CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Another reason is that the flattening time is a function of the overflow thickness

Method used

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  • Method of forming planar Cu interconnects without chemical mechanical polishing
  • Method of forming planar Cu interconnects without chemical mechanical polishing
  • Method of forming planar Cu interconnects without chemical mechanical polishing

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[0026] The method of the present invention provides a method of planarizing Cu interconnects with minimal mechanical stress on the surrounding dielectric and also provides a method of improving recrystallization in narrow interconnect structures. That is, the method of the present invention provides planarized Cu interconnects without the use of CMP. Referring to FIG. 1 , like all figures, which is for illustration purposes only and not drawn to scale, shows a partially filled copper interconnect in a dielectric. Narrow and wide interconnect structures 7, 10 disposed in the dielectric 5 are shown. The copper interconnect structure in Figure 1 is plated using a plating solution. More specifically, an acid plating solution is used to form partially filled copper interconnect structures. It can be seen (see narrow and wide interconnect structures 7 and 10 respectively) that copper fills narrow interconnect structures faster than wide interconnect structures. In the current sta...

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Abstract

A method for controlling the shape of copper features, having the following steps: a) plating a copper feature with a predetermined final shape onto a copper seed layer in a plating bath for a first plating time using a first plating method, wherein the first plating time is less than the total length of time necessary to plate the substantially all of the final shape; and b) electrically treating the plated copper feature in a copper plating bath for a second period of time, the second period of time sufficient to at least form the predetermined final shape.

Description

technical field [0001] The present invention relates generally to semiconductors, and more particularly to copper plating and planarization. Background technique [0002] In the manufacture of integrated circuits, after individual devices (eg, transistors) are fabricated in a substrate, they must be connected together to achieve the desired circuit function. This connection process is commonly referred to as an interconnect metallization process and is accomplished using a number of different photolithography and deposition techniques. [0003] One method used to accomplish the line / via interconnect metallization process is called the dual damascene method. Photolithography and reactive ion etching methods are used to shape the lines and vias before the lines or vias are filled by a metallization process. The lines and vias are then filled with the desired metallization process. The metal that fills the lines and vias is copper, and additional steps must be taken before f...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/3205C25D5/18C25D7/12H01L21/288H01L21/321H01L21/3213
CPCH01L21/7684C25D5/18C25D7/123H01L21/32115H01L21/2885H01L21/76879C25D7/12H01L21/32134
Inventor 徐顺天曾伟志D·D·雷斯塔伊诺J·E·弗吕格尔R·O·亨利J·M·科特M·克里希南H·德利吉安尼P·M·韦雷肯S·E·格雷科
Owner INT BUSINESS MASCH CORP