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Computational processor

A computing processing device and technology for computing data, which are applied in the fields of electrical digital data processing, digital data processing components, computing, etc., and can solve the problems such as the inability to realize cheap portable terminals, the inability to be monolithic, and the increase in cost.

Inactive Publication Date: 2001-06-20
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, it exceeds the processing capability of the existing DSP, making it impossible to achieve single-chip by DSP
If the DSP is increased in performance to increase the amount of calculation, the cost of the DSP itself will increase, and as a result, it will not be possible to reduce the cost of portable terminals.

Method used

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Examples

Experimental program
Comparison scheme
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Embodiment 1

[0035] figure 2 is a block diagram showing the configuration of the arithmetic processing device of this embodiment.

[0036] exist figure 2 Among them, it mainly includes: operation data storage unit 101, which stores operation data; input data storage unit 102, which stores input data; generator polynomial storage unit 103, which stores coefficients of generator polynomial; arithmetic units 104, 105, carry out modulo 2 addition; and select The unit 106 outputs either one of the two input data.

[0037] Hereinafter, a case of a 3-bit CRC will be taken as an example to specifically describe the processing performed by each component.

[0038] In the case of an N-bit CRC, the operation data storage unit 101 and the generator polynomial storage unit 103 need to be composed of at least N bits, and the arithmetic unit 105 needs to be able to perform at least N-bit modulo 2 addition. For example, in the case of a 3-bit CRC, the operation data storage unit 101 and the generator...

Embodiment 2

[0052] Figure 4 is a block diagram showing the configuration of the arithmetic processing device of this embodiment. exist Figure 4 in, right with figure 2 The same components are appended with figure 2 The same reference numerals are used, and descriptions thereof are omitted.

[0053] Figure 4 The arithmetic processing device shown with the figure 2 Compared with the arithmetic processing device shown, the configuration in which the arithmetic units 104 and 105 are replaced by the addition of selection units 201 and 202 , the arithmetic unit 203 and the arithmetic result storage unit 204 is employed.

[0054] Figure 4 The arithmetic processing device shown is carried out with arithmetic unit 203 figure 2 In the processing of the two arithmetic units 104 and 105 in the shown arithmetic processing device, a CRC operation is performed for each bit in two machine cycles. The selection unit 201 and the selection unit 202 switch the data input to the arithmetic uni...

Embodiment 3

[0062] Figure 5 is a block diagram showing the configuration of the arithmetic processing device of this embodiment. exist Figure 5 in, right with figure 2 The same components are appended with figure 2 The same reference numerals are used, and descriptions thereof are omitted.

[0063] Figure 5 The arithmetic processing device shown with the figure 2 Compared with the arithmetic processing device shown, the arithmetic unit 301 is added instead of the arithmetic units 104 and 105 .

[0064] Figure 5 The arithmetic processing device shown is carried out by using the arithmetic unit 301 figure 2 In the processing of the two arithmetic units 104 and 105 in the arithmetic processing device shown, two types of data are merged and then operated, and the CRC operation is performed for each bit in one machine cycle.

[0065] Hereinafter, a case of a 3-bit CRC will be taken as an example to specifically describe the processing performed by each component.

[0066] In t...

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PUM

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Abstract

A functional unit (104) carries out mod2 addition of MSB of operation data stored in an operation data storage section (101) and input data stored in an input data storage section (102). A functional unit (105) carries out mod2 addition of data created by shifting the operation data by one bit to the MSB side and the coefficient of a generating polynomial stored in a generating polynomial storage section (103). A selection section (106) selects either the shifted data or the result of operation by the functional unit (105) according to the result of the operation by the functional unit (104) and stores the selected one as operation data in the operation data storage section (101). In such a way, CRC operation by DSP is efficiently performed with a little investment.

Description

technical field [0001] The present invention relates to an arithmetic processing device for performing CRC calculation mounted on wireless communication equipment or the like. Background technique [0002] In wireless communication, in order to correct bit errors that occur during wireless transmission, encoding processing for error correction is performed on data at the transmitting end, and decoding processing is performed on error correction codes at the receiving end. [0003] However, when the propagation environment is harsh and errors occur extremely frequently, it is difficult to completely correct errors only by the above-mentioned error correction processing. Therefore, in mobile radio communication, error detection processing is performed in addition to the above-mentioned error correction processing to detect whether or not an error remains. A representative error detection process includes CRC (Cyclic Redundancy Check, Cyclic Redundancy Check). [0004] Herein...

Claims

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Application Information

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IPC IPC(8): G06F11/10G06F7/72H03M13/00H03M13/09H04L1/00
CPCH04L1/0061H03M13/09H03M13/6569H04L1/0043G06F7/724
Inventor 山中隆太郎惣门淳二户田隆
Owner PANASONIC CORP
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