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Chip packaging structure and chip and subtrate electric connection structure

A chip packaging structure, electrical connection structure technology, applied in the direction of circuits, electrical components, electrical solid devices, etc., can solve the problems of large transmission line system impedance, chip 110 operation error, signal reflection, etc., to achieve the effect of avoiding chip operation errors

Inactive Publication Date: 2007-05-16
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, since the cross-sectional area of ​​the signal wire bonding wire 130a is very small and the length is very long, the signal wire bonding wire 130a will generate high impedance when transmitting a high-frequency signal, so that the impedance of the transmission line via the signal wire bonding wire 130a will decrease. The deviation from the system impedance is relatively large, resulting in serious signal reflection, and even serious cases will cause chip 110 calculation errors

Method used

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  • Chip packaging structure and chip and subtrate electric connection structure
  • Chip packaging structure and chip and subtrate electric connection structure
  • Chip packaging structure and chip and subtrate electric connection structure

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Embodiment Construction

[0057] first preferred embodiment

[0058] Fig. 3 shows a cross-sectional view of a chip package structure in which a chip is electrically connected to a lead frame by wire bonding according to a first preferred embodiment of the present invention; Fig. 4 shows a connection between a chip and a substrate according to a first preferred embodiment of the present invention A perspective view of the electrical connection structure; FIG. 5 shows a top view of the electrical connection structure between the chip and the substrate according to the first preferred embodiment of the present invention.

[0059] 3, 4 and 5, the chip package structure 200 includes a chip 210, a lead frame 220, a wire bonding wire 230, a characteristic wire bonding wire 232a, 232b, a grounding wire bonding wire 240 and an insulating material 250, and the lead frame 220 has a chip holder 222, a plurality of common pins 224 with the same shape and at least one characteristic pin structure 226. In this embodi...

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Abstract

The structure comprises a wire rack, a chip, multiple joint wires for lead wires, at least a joint wire for characteristic lead wire and insulation material. The wire rack possesses a chip seat, multiple general pins structure and a characteristic pin structure. General pins structure and a characteristic pin structure between general pins are arranged around chip seat. Sectional area of characteristic pin structure is larger than sectional area of general pin structure. The said both sectional areas are perpendicular to transmission direction of signal. Chip is seated in chip seat. Joint wires for lead wires are connected between chip and general pins, and joint wire for characteristic lead wire is connected between chip and characteristic pin structure. Using the joint wire for characteristic lead wire transfers same signal. Insulation material covers wire rack, chip, multiple joint wires for lead wires, and joint wire for characteristic lead wire.

Description

technical field [0001] The invention relates to a chip packaging structure and an electrical connection structure between the chip and a substrate, and in particular to a chip packaging structure with high electrical performance and an electrical connection structure between the chip and the substrate. Background technique [0002] In today's information society, high-speed, high-quality, and multi-functional products are all pursued, and in terms of product appearance, the trend is towards light, thin, short, and small. General electronic products have a semiconductor chip and a carrier electrically connected to the semiconductor chip. Today, the industry generally uses three technologies to electrically connect the chip to the carrier. The first is wire-bonding; the second is Flip-chip process (flip-chip); the third is the flexible tape automatic connection process (tape-automated-bonding, TAB). When the carrier adopts a lead frame, the chip is generally electrically conn...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/48H01L21/60
CPCH01L2224/0603H01L2924/01082H01L2924/3011H01L24/05H01L2224/32245H01L2224/48247H01L24/06H01L2924/01005H01L2924/01033H01L2924/01006H01L2224/05552H01L2224/49112H01L2224/48091H01L2224/73265H01L2924/3025H01L24/49H01L2224/04042H01L2224/48257H01L2924/30111H01L24/73H01L2924/181H01L2224/49H01L2924/00014H01L2924/00012H01L2924/00
Inventor 李胜源许志行
Owner VIA TECH INC