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Chip packaging structure and chip and subtrate electric connection structure

A technology of chip packaging structure and electrical connection structure, applied in circuits, electrical components, electrical solid devices, etc., can solve the problems of large impedance, signal reflection, and high impedance of transmission line systems, and achieve the effect of avoiding chip operation errors.

Active Publication Date: 2004-09-15
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the cross-sectional area of ​​the signal wire bonding wire 130a is very small and the length is very long, the signal wire bonding wire 130a will generate high impedance when transmitting a high-frequency signal, so that the impedance of the transmission line via the signal wire bonding wire 130a will decrease. The deviation from the system impedance is relatively large, resulting in serious signal reflection, and even serious cases will cause chip 110 calculation errors

Method used

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  • Chip packaging structure and chip and subtrate electric connection structure
  • Chip packaging structure and chip and subtrate electric connection structure
  • Chip packaging structure and chip and subtrate electric connection structure

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Embodiment Construction

[0057] first preferred embodiment

[0058] image 3 A cross-sectional view showing a chip package structure in which the chip is electrically connected to the lead frame by wire bonding according to the first preferred embodiment of the present invention; Figure 4 A perspective view showing the electrical connection structure between the chip and the substrate according to the first preferred embodiment of the present invention; Figure 5 A top view showing the electrical connection structure between the chip and the substrate according to the first preferred embodiment of the present invention.

[0059] Please refer to image 3 , Figure 4 and Figure 5 The chip packaging structure 200 includes a chip 210, a lead frame 220, a wire bonding wire 230, a characteristic wire bonding wire 232a, 232b, a grounding wire bonding wire 240 and an insulating material 250, and the lead frame 220 has a chip holder 222, a plurality of identically shaped The general pin 224 and at least...

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Abstract

The structure comprises a wire rack, a chip, multiple joint wires for lead wires, at least a joint wire for characteristic lead wire and insulation material. The wire rack possesses a chip seat, multiple general pins structure and a characteristic pin structure. General pins structure and a characteristic pin structure between general pins are arranged around chip seat. Sectional area of characteristic pin structure is larger than sectional area of general pin structure. The said both sectional areas are perpendicular to transmission direction of signal. Chip is seated in chip seat. Joint wires for lead wires are connected between chip and general pins, and joint wire for characteristic lead wire is connected between chip and characteristic pin structure. Using the joint wire for characteristic lead wire transfers same signal. Insulation material covers wire rack, chip, multiple joint wires for lead wires, and joint wire for characteristic lead wire.

Description

technical field [0001] The invention relates to a chip packaging structure and an electrical connection structure between the chip and a substrate, and in particular to a chip packaging structure with high electrical performance and an electrical connection structure between the chip and the substrate. Background technique [0002] In today's information society, high-speed, high-quality, and multi-functional products are all pursued, and in terms of product appearance, the trend is towards light, thin, short, and small. General electronic products have a semiconductor chip and a carrier electrically connected to the semiconductor chip. Today, the industry generally uses three technologies to electrically connect the chip to the carrier. The first is wire-bonding; the second is Flip-chip process (flip-chip); the third is the flexible tape automatic connection process (tape-automated-bonding, TAB). When the carrier adopts a lead frame, the chip is generally electrically conn...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60H01L23/48
CPCH01L2224/0603H01L2924/01082H01L2924/3011H01L24/05H01L2224/32245H01L2224/48247H01L24/06H01L2924/01005H01L2924/01033H01L2924/01006H01L2224/05552H01L2224/49112H01L2224/48091H01L2224/73265H01L2924/3025H01L24/49H01L2224/04042H01L2224/48257H01L2924/30111H01L24/73H01L2924/181H01L2224/49H01L2924/00014H01L2924/00012H01L2924/00
Inventor 李胜源许志行
Owner VIA TECH INC