High speed synchronous counter

Abstract

The counter possesses input lines for counting signal and n bits counting stage, N is larger than o r equal to 2. Characters are that each bit in counting circuit possesses a counting circuit and at least a counting preset unit. Counting circuit possesses at least one counting preset input port. Each counting preset unit possesses at least two input end and at least one output end. The input end of the counting preset unit is connected to output end of this stage as well as output ends of all previous counters. Output end of counting preset unit is connected to counting preset input port of counter in this stage. Delay time of counting preset unit in each counter is identical. Counter for each bit is run in parallel. Thus, the invention reaches higher counting speed and synchronizing precision for parts and device in same speed, provides wider range for frequency of counting input signal.

Description

technical field [0001] The invention belongs to the field of digital circuits, and in particular provides a high-speed synchronous counter, which can improve counting speed and synchronization precision. Background technique [0002] Commonly used counters use the output of the counter at the previous stage as the counting input of the counter at the next stage. The counters at all levels are connected in series. The total delay of the counter is equal to the sum of the delays of the counters at all levels. Synchronous. This type of counter is only suitable for applications that do not require high counting speed and synchronous counting, and its typical circuit is the circuit used by the 7493 chip. [0003] US Patents 3,943,478 and 4,679,216 disclose a synchronous binary counter which incrementally gates the output signals of all preceding stages to the input signals of subsequent stages. However, the repeated use of each level complicates the input of the "NAND" gate use...

AI Technical Summary

Problems solved by technology

[0006] The counting state is transmitted serially. When the number of counter stages is large, the total delay time is longer; the clock frequency of the input line can only be within a certain range, neither too high nor too low, and the frequency range depends on the speed of the circuit device , the frequency range of devices with different speeds is different; the synchronous speed of each counter counting is low

This counter is not suitable for high-speed counting and high-speed readout applications, such as high-speed timers

The counter also cannot be used in applications where the clock pulse interval of the input line varies over a wide range, such as random timers

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