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High speed buffer memory conversion method

A high-speed cache and counter technology, applied in memory systems, memory address/allocation/relocation, instruments, etc., can solve the problems of inability to improve the coincidence rate of the cache area, and the inability to take into account the access time and access times at the same time, to achieve Improve the matching rate of the cache area and improve the performance of data access

Inactive Publication Date: 2007-06-20
MITAC COMP (SHUN DE) LTD +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, no matter whether the LRU or LFU method is used as the cache replacement method, the factors of access time and access times cannot be taken into account at the same time, resulting in the inability to increase the hit rate of the cache area for data access.

Method used

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Embodiment Construction

[0017] Hereinafter, the cache replacement method of the present invention will be described in detail by taking a cache used in a redundant array of inexpensive disks (Redundancy Array of Inexpensive Disk, RAID for short) as an example. Certainly, as those skilled in the art should know, the numbers representing the memory capacity or field width in the embodiments are only for easy understanding during explanation, and are not necessarily limited in this way. The actual application depends on the requirements of the system, and the present invention is not limited to be used only in the RAID system.

[0018] Please refer to FIG. 1 , which is a schematic diagram of a RAID structure according to a preferred embodiment of the present invention. As shown in the figure, the RAID 100 is composed of 16 independent hard disk drives 101-116. Each hard disk drive 101-116 is divided into 64K pages, and each page is further divided into 4K caches. Each cache line includes 8 blocks, and ...

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Abstract

The cache substituting algorithm has one time counter applied to maintain one time relative value, and each time the quick arean of the cache is accessed, the value in the time counter is added to the weigh counter of the corresponding quick area. Therefore, referring the value in the weigh counter to decide whether to substitute the quick arean is favorable to access time, access time number and other factors and can raise the access coincidence rate of the quick arean in the cache and raise datan access efficiency.

Description

technical field [0001] The present invention relates to a cache, and more particularly to a cache replacement algorithm. Background technique [0002] A cache is a small, fast memory used in storage media to increase its access speed. Because its access rate is faster than the main memory used by the storage medium, when the processor wants to access addresses, instructions, and data from the storage medium, if it can be accessed from the cache, its speed will be faster than that of the main memory. Direct access in memory is fast and efficient, so a cache is often thought of as a buffer memory for main memory. [0003] However, due to cost considerations, the capacity of the cache cannot be expanded indefinitely. Taking a 4 megabyte (4TBytes) cheap disk redundant array (Redundancy Array of Inexpensive Disk, referred to as RAID) as an example, the cache used is usually But it is 512M Bytes, or even lower. Obviously, the data it can store is extremely limited compared to t...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08G06F12/0877
Inventor 简荣成卓维强
Owner MITAC COMP (SHUN DE) LTD