Network equipment and method for distributing its peripheral device interconnection resources
A technology of network equipment and allocation method, which is applied in the direction of data exchange network, instruments, electrical components, etc., can solve the problems of inconvenient management, non-uniform allocation of memory space and waste of storage space, and achieve the effect of avoiding waste and simplifying memory management
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[0037] The PCI bus architecture is a hierarchical architecture. As shown in Figure 1, the CPU is connected to the main PCI bus -- bus 0 through the Host-PCI bridge. Except for position M, position 1 to position N are each PCI interface on the bus 0. The PCI interface is the connection interface reserved on the bus to be connected to the PCI device. It is usually a PCI slot for inserting an expansion card, or it may be other conforming The connection interface of the PCI specification. At the position M, the PCI bridge connects the bus L and the bus 0. At this time, the bus 0 is the upstream bus of the PCI bridge, and the bus L is the downstream bus of the PCI bridge. Positions (N+1) to (N+K) are PCI interfaces on bus L. Each free PCI interface in the figure can be used to connect PCI devices, which can be a single PCI device, or a combination of more than one PCI device, or a PCI bridge device, including a PCI bridge and on its downstream bus A PCI device is connected.
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