Storage device array magnetic bit with of with sharing one common line

Abstract

A data storage device (10) having parallel memory planes is disclosed. Each memory plane comprises a first resistive cross-point plane (108a) of a memory cell, a second resistive cross-point plane (108b) of a memory cell, a plurality of conductive strips shared between the first and second planes of memory cells A word line (102), a plurality of bit lines (104), wherein each bit line connects one or more cells from a first plane to another memory cell in a second plane, and a plurality of unidirectional cells (110 ). In addition, a unidirectional cell connects a first memory cell from the first plane to a selected word line and a selected bit line along a first conductive direction, and a second unidirectional cell connects a second memory cell from the first plane to a selected bit line along a second conductive direction. A second cell of the two planes to a selected word line and a selected bit line. The device further provides a unidirectional conductive path from a memory cell in the first plane to a memory cell in the second plane sharing the same bit line.

Description

technical field [0001] The present invention relates to the field of resistive memory cell arrays. More particularly, this invention relates to a memory array having pairs of memory bits sharing a common conductor for increased array density. Background technique [0002] A resistive random access memory (RAM) is a cross-point type memory array of spaced memory cells sandwiched between two grids of wires running in an orthogonal direction above or below the cell a flat matrix. The resistive RAM array 10 shown in FIG. 1 is an example. Row conductors 12 running in one direction are called word lines, and column conductors 14 running in a second direction, generally perpendicular to the first direction, are called bit lines. The memory cells 16 are typically arranged in a square or rectangular array such that each memory cell 16 is connected to a word line 12 and an intersecting bit line 14 . [0003] In a resistive RAM array, the resistance of each memory cell has more tha...

AI Technical Summary

Problems solved by technology

This action isolates the bit line currents from each other, effectively blocking most of the leakage current that would otherwise flow through the secondary channel, potentially causing errors in the sense function of the selected memory cell.

[0008] Several problems associated with all memory arrays are the need to simplify the structure, the desire to increase memory storage density, and the need to reduce the number of wires within the array

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