Circuit and method for supplying page mode operation in semiconductor storing device

Abstract

A semiconductor memory device having a partial activation framework, which provides an efficient page mode operation while operating in a partial activation mode. Control circuits and methods are provided to enable a page mode operation (for read and write data accesses) in a semiconductor memory device (such as a DRAM, FCRAM) having a partial activation framework, resulting in an improved data access speed when data is written / read from memory locations having the same wordline address. In one aspect, a method for accessing data in a memory device comprises activating a first wordline corresponding to a first address to perform a data access operation, receiving a second address after the first address, if the second address is the same as the first address, generating a page mode enable signal for maintaining an activated state of the first wordline corresponding to the first address while activating a second wordline corresponding to the second address, and deactivating the first and second wordlines in response to disabling of the page mode enable signal.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 2002-61042 filed on October 10, 2002 at the Korean Intellectual Property Office, which is incorporated herein by reference. technical field [0003] The present invention relates to a circuit and method for providing page mode operation in a semiconductor memory device having a partially active structure. Background technique [0004] There has long been a need for semiconductor devices such as DRAM (Dynamic Random Access Memory) devices that provide fast and efficient memory access operations (read and write operations). But as the memory access speed of DRAM increases, power dissipation usually increases, which can cause serious problems. Therefore, operating speed and power dissipation are generally considered trade-off relationships when developing semiconductor memory devices. Certain techniques for controlling power dissipation while providing ...

AI Technical Summary

Problems solved by technology

Traditional DRAM devices operate in "page mode" to increase memory access speed while reducing power consumption

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