Circuit and method for supplying page mode operation in semiconductor storing device
A mode and page technology, applied in the field of circuits and methods providing page mode operation in semiconductor storage devices
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[0036] The present invention is a semiconductor memory device that provides effective page operation in a partially activated operation mode. Specifically, the circuit and method of the preferred embodiment of the present invention are based on addressing schemes and control circuits that provide improved page mode operation and increase the data access speed of semiconductor memory devices (such as DRAM, FCRAM) with a partially activated structure.
[0037] image 3 It is a block diagram illustrating a semiconductor memory device with a partially activated structure according to an embodiment of the present invention, which provides a valid page mode operation in a partially activated operating mode. See image 3 , The semiconductor memory device includes: a memory cell array (100); a plurality of peripheral circuits (110 to 196) that input / output data to / from the memory cell array (100); a row address comparator (200); a command shifter ( 300). For illustrative purposes, it is ...
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