Semiconductor memory device
A non-volatile storage, data readout technology, applied in read-only memory, information storage, static memory, etc., can solve the problems of ensuring data readout margin, increasing circuit, etc. Effect
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Embodiment 1
[0036] refer to figure 1 , the MRAM device 1 shown as a representative example of the non-volatile memory device in Embodiment 1 of the present invention includes: a control circuit 5 that controls the overall action of the MRAM device 1 in response to the control signal CMD, and each has a matrix arrangement MTJ memory cells MC are multiple memory banks 10 of memory array MA. The memory bank 10 includes memory arrays MA0 to MAk (k: a natural number), and the memory array MA is a general designation of each memory array.
[0037] Moreover, as can be seen from the following description, the application of the present invention is not limited to MRAM devices provided with MTJ memory cells, and it is commonly applicable to non-volatile memory cells provided with a current corresponding to the level of stored data to be written. Lost storage device.
[0038] Here, the rows and columns of the plurality of memory cells MC integrally arranged in a matrix on each memory array MA are...
Embodiment 2
[0118] In the first embodiment described above, the configuration in which the control signals SAE and / SAE are input to the sense amplifier SA0 at approximately the same timing as the input to the sense amplifier SA to activate the sense amplifier SA0 is described.
[0119] Embodiment 2 of the present invention describes a configuration in which control signals SAE, / SAE are input to sense amplifier SA0 at different timings.
[0120] use Figure 12 The operation of the sense amplifier SA0 according to the second embodiment of the present invention will be described in the timing chart of FIG.
[0121] Although not shown, but with Example 1 Figure 9 Similarly, after a valid address ADD is input at time t1, control signal / SAE is set to L level at time t2. Accordingly, the transistor QPS of the sense amplifier SA0 is turned on, and the local input / output lines LIO, / LIO start to be charged to a predetermined voltage level. Then, at time t3, the column selection line CSLj, t...
Embodiment 3
[0135] In the above-mentioned first embodiment, the structure of the data read system circuit for performing 1-bit data read using the sense amplifier SA0 corresponding to the selected memory array MA0 has been described.
[0136] In Embodiment 3 of the present invention, the configuration of a data readout system circuit capable of parallelly reading multi-bit data will be described.
[0137] refer to Figure 14 , the data readout system circuit according to Embodiment 3 of the present invention includes a memory array MA#0 instead of the memory array MA0.
[0138] Here, a circuit group for data read operation provided corresponding to memory array MA#0 included in the input / output control circuit according to Embodiment 3 of the present invention is shown. As an example, only the memory array MA#0 will be described. The same is true for other storage arrays, so descriptions thereof will not be repeated.
[0139] In the memory array MA#0, there are a plurality of memory ce...
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