Semiconductor memory device
A storage device and semiconductor technology, applied in the fields of semiconductor devices, information storage, semiconductor/solid-state device manufacturing, etc., can solve the problems of inability to respond, inability to access the port unit at the same time, etc.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0047] (whole structure)
[0048] figure 1 It is a block diagram showing the structure of the semiconductor memory device according to Embodiment 1 of the present invention.
[0049] As shown in the figure, a 1-port memory cell array 11 (first memory cell array) and a 2-port memory cell array 12 (second memory cell array) are mixed and arranged on a single chip to constitute a memory macro. That is, the first port word line WL1 (first word line (common word line)) is provided in the 1-port memory cell array 11, and the first port word line WL1 (second word line (common word line)) is provided in the 2-port memory cell array 12. common word line)) and the second port word line WL2 (third word line).
[0050] The control circuit 31 receives the address input bus signal AD1, and supplies the row address to the row decoder 16 (the first row decoder) under the timing control of the read control input signal RE1 and the write control input signal WE1, and supplies the row address ...
Embodiment 2
[0145] Figure 8 is a block diagram showing the structure of a semiconductor memory device according to Embodiment 2 of the present invention. In the semiconductor storage device of Embodiment 2, a single-chip semiconductor storage device is realized by using a memory macro 60 (first memory cell array) with a 1-port memory cell structure and a memory macro 70 (second memory cell array) with a 2-port memory cell structure. .
[0146] As shown in the figure, it is realized by a combination of independently provided memory macros 60 and 70 . The memory macro 60 is composed of a 1-port memory cell array 61 , a row decoder 62 , a control circuit 63 and a column selector 64 . The first port word line WL1 (first word line) is provided in the 1-port memory cell array 61, and the first port word line WL21 (second word line) and the second port word line are provided in the two-port memory cell array 71. WL22 (3rd word line).
[0147] The control circuit 63 receives the addre...
Embodiment 3
[0164] Figure 9 is a block diagram showing the structure of a semiconductor memory device according to Embodiment 3 of the present invention.
[0165] As shown in the figure, a 1-port memory cell array 11L (first memory cell array) and a 2-port memory cell array 12R (second memory cell array) are mixedly arranged on a single chip, and a row decoder 18 (first row decoder) are sandwiched in between to form a memory macro. The first port word line WL1L (first word line) is provided in the 1-port memory cell array 11L, and the first port word line WL1R (second word line) and the second port word line are provided in the two-port memory cell array 12R. WL2 (3rd word line).
[0166] The row decoder 18 drives the word lines WL1L and WL1R for the first port to bring the same row into a common active state. Other composition and figure 1 Example 1 shown is the same.
[0167] In this way, in Embodiment 3, the control of the active state of the word lines WL1L and WL1R fo...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More