Synchronous to asynchronous to synchronous interface

Abstract

An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.

Description

technical field [0001] The present invention relates to data transfer, and more particularly, to systems and methods for transferring data via a synchronous-to-asynchronous-to-synchronous interface. Background technique [0002] Interlocked Pipeline Complementary Metal Oxide Semiconductor (IPCMOS) circuits and techniques are disclosed in US Patent 6,182,233. An article describing the results of the application of these IPCMOS circuits in a test field can be found in Logic and Systems published in the ISSCC2000 Technical Digest Volume 17, WA17.3, by Schuster et al., entitled "3.3-4.5GHz Asynchronous interlock pipeline CMOS circuit", hereinafter referred to as ISSCC article. In this ISSCC article, using 0.18 micron 1.5V bulk CMOS technology, asynchronously interlocked locally generated clocks at frequencies up to 4.5GHz drive a path through a 3-to-2 compressed tree. It is estimated that with these IPCMOS technologies, the power can be reduced by more than 2 times. [0003]...

AI Technical Summary

Problems solved by technology

However, it can be difficult to interface between synchronous and asynchronous parts of the system

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