Phase detector

Abstract

A phase detector is used to detect the phase difference between a data signal and a clock signal, and to export a first rising signal whose pulse width is between 1 / 2 times to 3 / 2 times of clock signal cycle, a first down signal having the same cycle as the clock signal, a second down signal and a second rising signal to a charging pump.

Description

Technical field [0001] The present invention relates to a phase detector (Phase Detector), in particular to a phase detector used in a phase-locked loop clock recovery system (Phase-locked Loop Clock Recovery System). Background technique [0002] For general synchronous transmission of digital signals, the data signal is transmitted from the transmitting unit to the receiving unit at a fixed rate. Generally, the receiving end uses a phase locked loop clock recovery system to detect the phase difference between the received data signal and the clock signal of the receiving end, and adjust the phase and frequency of the clock signal of the receiving end. In this way, the clock signal of the receiving end can have the same phase and the same frequency as the received data signal, so that the receiving end can sample and demodulate the data signal. [0003] Please refer to figure 1 , figure 1 Shows a block diagram of a conventional PLL clock recovery system. The conventional phase...

AI Technical Summary

Problems solved by technology

[0012] In view of this, the purpose of the present invention is to provide a phase detector, which can effectively solve the problem of traditional phase detectors that cause phase error signals to diverge and make the phase-locked loop clock recovery system unable to lock

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