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Logic computing system and method

A technology for logical calculation and configuration data, applied in the field of computing systems, which can solve the problems of reducing system processing capacity, high cost, and difficulty in frequently changing logical functions.

Inactive Publication Date: 2005-07-06
TOKYO ELECTRON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Updates of configuration data in conventional FPGAs result in prohibitive costs, thus reducing overall system processing capacity
Thus, it is difficult to frequently change logic functions in computing systems using conventional FPGAs
The invariance of logic functions limits the size of the programs that can be executed by the system

Method used

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  • Logic computing system and method
  • Logic computing system and method
  • Logic computing system and method

Examples

Experimental program
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Embodiment Construction

[0087] Fig. 1 shows the structure of a computing system 101 according to a first embodiment of the present invention. The computing system 101 shown in FIG. 1 is a programmable logic unit. The computing system 101 includes an FPGA data storage 2, a loader 3, and an FPGA device 4.

[0088] The FPGA data memory 2 stores a plurality of FPGA data modules 2-1 to 2-n. The compiler 6 provided outside the computing system 101 compiles a plurality of source programs 5-1 to 5-n to generate FPGA data modules 2-1 to 2-n. The compiler 6 may be included in the computing system 101. Use the hardware description language to program the source programs 5-1 to 5-n. For example, FPGA data modules 2-1 to 2-n are generated by compiling the source program 5-1. The FPGA data module 2-2 is generated by compiling the source program 5-2, and the same is true for the remaining FPGA data modules. Each FPGA data module 2-1 to 2-n is a configuration data module including data for forming a look-up table (LUT)....

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Abstract

The FPGA data blocks referenced as LUTs by logic block 43 are divided into blocks. Each of the plurality of data registers (41a-41d) stores one of the plurality of FPGA data blocks. The gates (43a) and flip-flops (43b) of the logic block (43) generate logic function values ​​of logic input data by referring to one or more FPGA data blocks stored in a plurality of data registers (41a-41d). Provides the logic function value of logic input data as logic output data.

Description

Technical field [0001] The present invention relates to a program that is directly executed by hardware, and particularly to a computing system suitable for executing large-scale programs. Background technique [0002] When a contemporary general-purpose computer executes an operation process, the CPU (central processing unit) continuously interprets multiple operation codes of the corresponding program. Multiple opcodes are stored in the memory to form software. Therefore, the program is implemented by the software. The structure of the CPU as the hardware cannot be optimized for the independent operation process contained in the software program. Therefore, the overhead is high during the operation process performed by the CPU. [0003] At the same time, as a technology for executing programs by hardware, PCT WO 94 / 10627 (Japanese Domestic Publication No. H8-504258) and PCT WO 98 / 08306 (Japanese Domestic Publication No. 2000-516418) disclose the use of FPGAs (field available Pr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/40G06F9/00G06F9/54G06F12/00G06F15/78H03K19/177
CPCG06F15/7867G06F9/00G06F9/06
Inventor 三田高司西原明法
Owner TOKYO ELECTRON LTD