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Apparatus and method for generating packed sum of absolute differences

A technology of absolute difference and sum, applied in the field of microprocessor computing operation, can solve problems such as long processing clock cycle

Active Publication Date: 2005-07-20
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this method has a disadvantage, that is, it will require a relatively long processing clock cycle to generate the above instruction results, especially for continuous addition operations.

Method used

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  • Apparatus and method for generating packed sum of absolute differences
  • Apparatus and method for generating packed sum of absolute differences
  • Apparatus and method for generating packed sum of absolute differences

Examples

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Embodiment Construction

[0034] Please refer to FIG. 1 , which shows a block diagram of an absolute difference command in a known multimedia extension technology. Wherein, reference numeral 100 represents a packed sum of absolute difference (PSADBW; packed sum of absolute difference) instruction in multimedia extension technology (MMX; multimedia extension). The block diagram 100 of the absolute difference packet sum instruction in the multimedia extension technology includes an instruction operation code 102 for specifying the absolute difference packet sum instruction in the multimedia extension technology, and two instruction operands 104 and 106 . Wherein, the first instruction operand 104 includes eight minuend operands (minuendoperand) of packed unsigned bytes, marked as X0 to X7. The second instruction operand 106 includes eight packed unsigned byte subtrahend operands, labeled Y0 through Y7.

[0035] In the multimedia extension technology, in the absolute difference packet sum instruction 100...

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Abstract

An apparatus for performing an MMX PSADBW instruction is disclosed. The apparatus includes carry-generating subtraction logic that generates packed differences of the subtrahend from the minuend and associated carry bits indicating whether the difference is positive or negative. The apparatus selectively inverts the differences based on the carry bits. Addition logic adds the selectively inverted differences and carry bits substantially in parallel to generate the PSADBW instruction result. In one embodiment, the apparatus also includes two muxes. The first mux selects the selectively inverted differences in the case of a PSADBW instruction and selects a multiply instruction's partial products otherwise. The second mux selects the carry bits in the case of a PSADBW instruction and selects a second multiply instruction's partial products otherwise. The two mux outputs are provided to the addition logic of the embodiment for the last calculation.

Description

[0001] Relevant information [0002] The application claims of this application are based on the previous U.S. Provisional Application No. 60 / 444531 (u.s.provisional, application, serial, No. 60 / 444531, filed January 31, 2003,) titled "APPARATUS AND METHOD FORGENERATING PACKED SUM OF AB SOLUTE DIFFERENCE", by. technical field [0003] The present invention relates to a method for calculating and operating a microprocessor, in particular to a method and device for generating the sum of absolute difference packages in the executable multimedia extension technology. Background technique [0004] The instruction set of the x86 architecture microprocessor includes a set of packed sum of absolute difference (PSADBW; packed sum of absolute difference) instructions. In the packed sum of absolute difference instruction, two 64-bit input operands are included, each of which is arranged as eight unsigned packed integer bytes (unsigned byte integers). Among the two 64-bit input operan...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/302
CPCG06F9/30036
Inventor 强森·丹尼尔路伯·亚伯特
Owner VIA TECH INC