Packet transfer circuit and packet transfer method

Abstract

Inputter 191 sorts and accommodates packets in a plurality of containers 193. Containers 193 contain the packets in a plurality queues 1931 in and from which the packets can be written and read. Read controller 194 has read queue information generator 1941 that, on a per container basis, generates read queue information indicating the queues that have the packets written therein, priority determiner 1940 that, on a per queue basis, determines the priorities in the reading of the packets, and read queue determiner 1942 that, on a per container basis, determines the queue to read the packets from with reference to the write queue information and the priorities.

Description

technical field [0001] The present invention relates to a packet transfer circuit and a packet transfer method for outputting packets stored in a plurality of queues. Background technique [0002] In recent years, a packet transfer device employing a VOQ (Virtual Output Queue) method has been used for improved throughput of the packet transfer device. [0003] A packet transfer device employing the VOQ method has a plurality of receivers for receiving packets and a plurality of transmitters for transmitting packets, and is designed to have received packets queued in VOQ provided in the receivers . [0004] More than one prior art type of packet transfer device is disclosed in Published Unexamined Japanese Patent Application No. 2001-7822. Such as figure 1 As shown, the packet transfer apparatus is provided with VOQMs (VOQ Modules) 3 each having a VOQ corresponding to the transmitter 2 in the receiver 1 . [0005] Such as figure 2 As shown, when a VOQ queues a packet, t...

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Problems solved by technology

[0023] Also, with the packet transfer device disclosed in Published Unexamined Japanese Patent Application No. 2001-7822, the number of time slots forming one frame is the same as the number of SMs, and thus the number of receivers and transmitters increases resulting in forming one frame The increase in the number of slots

That is, with the packet transfer device disclosed in Published Unexamined Japanese Patent Application No. 2001-7822, the number of receivers and transmitters is increased, then time extension of one frame occurs, and each SM determines that it will output The time spent on a packet's VOQ also extends during which packets are not output from that VOQ, which then leads to the problem of increased latency

[0024] Also, the packet transfer device disclosed in Published Unexamined Japanese Patent Application No. 2001-168869 is configured so that the search of the output queue starts only after reading information from two types of tables, and therefore the queue searcher 78 has to Waiting until the read from both types of tables ends, which then leads to the problem of increasing the time used to determine the queue

In addition, with the packet transfer device disclosed in Published Unexamined Japanese Patent Application No. 2001-168869, there is a problem that it is necessary to provide means for starting the operation of the WRR scheduler 19 before outputting the packet from the queue.

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