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Manufacturing method of two-wine structure film transistor array

A technology of thin film transistors and manufacturing methods, which is applied in the fields of transistors, semiconductor/solid-state device manufacturing, nonlinear optics, etc., and can solve problems such as the inability to apply double-conductor structures and expensive lithography processes

Inactive Publication Date: 2006-01-25
AU OPTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, since the lithography process is very expensive, the number of required masks must be kept as low as possible
Although a four-step lithography process has

Method used

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  • Manufacturing method of two-wine structure film transistor array
  • Manufacturing method of two-wine structure film transistor array
  • Manufacturing method of two-wine structure film transistor array

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0027] Please refer to Figure 2a -2d The flow chart of a preferred embodiment of the manufacturing method of the double-wire structure thin film transistor array of the present invention, and Figures 3a-3c A cross-sectional flowchart of a thin film transistor in a preferred embodiment of the present invention. Figure 2a -2d is along Figure 4 A cross-sectional view of line I-I in the top view of the thin film transistor array of the present invention, Figures 3a-3c is along Figure 4 Cross-sectional flow chart of a thin film transistor crossed at the position of the middle line II-II. Such as Figure 2a As shown, first a first metal layer 20 with a first pattern is deposited on the glass substrate 10, and a scanning line 21 and a thin film transistor gate of an active liquid crystal display are formed on the first metal layer 20. pole electrode 22 (see Figure 3a ). Next, the insulating layer 30, the semiconductor layer 35, the ohmic contact layer 40, and the second...

Embodiment 2

[0029] Please refer to Figure 2a -2d, the flow chart of a preferred embodiment of the manufacturing method of the double-wire structure thin film transistor array of the present invention, and Figures 3a-3c A cross-sectional flowchart of a thin film transistor in a preferred embodiment of the present invention. Figure 2a -2d is along Figure 4 A cross-sectional view of line I-I in the top view of the thin film transistor array of the present invention, Figures 3a-3c is along Figure 4 Cross-sectional flow chart of a thin film transistor crossed at the position of the middle line II-II. Such as Figure 2a As shown, first a first metal layer 20 with a first pattern is deposited on the glass substrate 10, and a scanning line 21 and a thin film transistor gate of an active liquid crystal display are formed on the first metal layer 20. pole electrode 22 (see Figure 3a ). Next, the insulating layer 30, the semiconductor layer 35, the ohmic contact layer 40, and the secon...

Embodiment 3

[0031] Please refer to Figure 2a -2d The flow chart of a preferred embodiment of the manufacturing method of the double-wire structure thin film transistor array of the present invention, and Figures 3a-3c A cross-sectional flowchart of a thin film transistor in a preferred embodiment of the present invention. Figure 2a -2d is along Figure 4 A cross-sectional view of line I-I in the top view of the thin film transistor array of the present invention, Figures 3a-3c is along Figure 4 Cross-sectional flow chart of a thin film transistor crossed at the position of the middle line II-II. Such as Figure 2a As shown, first a first metal layer 20 with a first pattern is deposited on the glass substrate 10, and a scanning line 21 and a thin film transistor gate of an active liquid crystal display are formed on the first metal layer 20. pole electrode 22 (see Figure 3a ). Next, the insulating layer 30, the semiconductor layer 35, the ohmic contact layer 40, and the second...

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Abstract

The invention relates to a method of making double wire structured thin film transistor array, including the following steps: firstly providing a substrate; then forming a first metal layer with a first pattern on the substrate; then in order depositing an insulating layer, a semiconductor layer, an ohm contact layer and a second metal layer on the substrate and forming a second pattern on the semiconductor layer, the ohm contact layer and the second metal layer; then forming a first protective layer with a third pattern on the second metal layer and simultaneously removes part of the insulating layer to form plural first contact windows; and finally forming a conductive layer connecting the two metal layers at the first contact windows.

Description

technical field [0001] The invention relates to a manufacturing method of a thin film transistor array, especially a method suitable for manufacturing a double metal structure thin film transistor array with a four-pass photomask process. Background technique [0002] At present, in the manufacture of large-scale liquid crystal display panels, due to the gradual reduction of line width and spacing, the connection resistance and the capacitance between the connections are indirectly caused by the increase, so the resistance-capacitance delay (RC-delay) effect occurs. There will be many negative effects on the circuit, and the signal transmission speed is the most serious. The simplest and most direct way to solve this problem is to try to reduce the resistance and capacitance. The double metal structure can effectively slow down the RC-delay effect. Its structure is two metal conductive lines separated by an insulating layer. The contact window between the two is formed by th...

Claims

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Application Information

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IPC IPC(8): G02F1/136H01L29/786H01L21/00G03F7/20
Inventor 张业成
Owner AU OPTRONICS CORP