Semiconductor memory system and method for data transmission between memory controller and semiconductor memory

Abstract

A semiconductor memory system is proposed in which the transfer of a burst of memory data (DQ) following the command/address data (CA) of a write/read command (WRITE) is marked with a modified clock signal (CLK). The modified clock signal (CLK) includes an identification region (3, 4) with masked clock edges, so the transfer of memory data (DQ) can be represented by a clock edge following the identification region (3, 4) .

Description

technical field [0001] The invention relates to a semiconductor memory system with a memory controller and a semiconductor memory and to a method for transferring memory data between the memory controller and the semiconductor memory, wherein the transfer of the memory data in bursts is represented by means of a clock signal . Background technique [0002] In future generations of memory, synchronization between instruction / address data (CA) and memory data (DQ) will become increasingly difficult as the length of the unit interval (UI) of bits of memory data (DQ) becomes Less than the expected fluctuation width of the clock signal for command / address data. For example, in the future DDR4 generation memory, it can be expected that the length of the unit interval of the bit of memory data is only 156 ps. Therefore, finding the first memory bit of a data burst that has a time relationship to a read or write command is difficult. The high data transfer rates of future memory ...

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Problems solved by technology

However, a freely oscillating clock signal brings with it the disadvantage that neither the start nor the end of a data burst can be identified with it

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