Circuit and method for test mode entry of a semiconductor memory device

Abstract

Provided are a circuit and method for a test mode entry of a semiconductor memory device. In the method of entering a semiconductor memory device into a test mode, an internal clock is generated in response to an external clock when a first condition is satisfied. An address combination signal is generated based on the first address combination and an internal clock. A semiconductor memory device is put into a test mode using a combined internal clock and address signal.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more particularly to a circuit and method for controlling entry into a test mode of the semiconductor memory device. Background technique [0002] Typically, a semiconductor memory device includes a test mode so that a test function can be performed by the device manufacturer. In order to perform test functions, such as functions associated with the reliability of a semiconductor memory device, the device is placed in a test mode. [0003] The test mode is an operation mode dedicated to testing semiconductor memory devices. With the exception of certain Mode Register Set (MRS) commands used to control device settings, the functionality of the test mode is not under user control. For example, MRS commands such as column address strobe (CAS) latency or pulse time can be controlled by the user. [0004] A semiconductor memory device generally includes a test mode entry circuit for cont...

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Problems solved by technology

[0027] For example, when the timing margin MG is reduced to zero, the address combination signals PAi1 and PAi2 to be sampled by the delayed clock PCLKP may transition, and thus it may be difficult to ensure the hold time and setup time for generating the test mode entry signals TENT1 and TENT2

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