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Class-D amplifier

A class D amplifier, adder technology, applied in amplifiers, improved amplifiers to reduce noise effects, amplifiers with semiconductor devices/discharge tubes, etc., can solve problems such as influence, sample signal jitter, and no feedback.

Inactive Publication Date: 2006-09-20
YAMAHA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But there is a problem that when PWM is performed by analog processing, it is easily affected by external signals and signals such as input digital data
However, since this class D amplifier uses ΔΣ modulation, it has the disadvantages of requiring a higher frequency and having low power efficiency
Also, there is another drawback: proper feedback cannot be performed because the feedback signal taken on the output of the constant voltage switch is asynchronous to the input clock
[0011] In the above class D amplifier, since the multiplier 4 composed of PLL is used, jitter tends to be generated to become output noise
There are many cases where the sampling signal supplied from the output side including noise also generates jitter

Method used

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Embodiment Construction

[0038] Embodiments of the invention will be described below with reference to the drawings.

[0039] figure 1 is a configuration diagram illustrating the configuration of the first embodiment of the class D amplifier according to the invention. In this figure, reference numeral 11 designates an input terminal for receiving PCM sound data PD ("sound" here means general sound including musical tones, not limited to human voice). Reference numeral 12 denotes an adder. Reference numeral 13 defines a PWM circuit that converts the sound data from the adder 12 into a PWM signal based on the carrier signal Pct. Reference numeral 14 defines a feedback circuit H(z) for suppressing quantization noise of the PWM circuit 13 . The output of the feedback circuit H(z) 13 is applied to the adder 12 . Reference numeral 15 denotes an output switching circuit whose output is applied to a load (speaker) via a low-pass filter. The above structure is the same as the structural parts 1, 2, 3 and...

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Abstract

A D class amplifier of the invention generates a carrier signal Pct based on a master clock Phip without jitter, which is supplied to a PWM circuit. Using a digital PLL including a phase comparator, a loop filter and a carrier oscillator, the generated carrier signal Pct is synchronized with a sampling signal SL. This can produce the carrier signal Pct that is not affected by the jitter contained in the sampling signal SL. Because a phase difference between the sampling signal SL and the carrier signal Pct is fedback to through a feedback circuit, jitter, which can be produced by a slight difference between the sampling signal SL and the master clock Phip can be eliminated.

Description

[0001] priority claim [0002] Priority is claimed from Japanese Patent Application No. 2005-079061 filed in the Japan Patent Office on Mar. 18, 2005, the contents of which are hereby incorporated by reference. field of invention [0003] The invention relates to a Class D amplifier that converts PCM (Pulse Code Modulation) sound (music tone) data into a PWM (Pulse Width Modulation) signal that is amplified and output, and more particularly to a Class D amplifier designed to reduce output noise. Background technique [0004] It is well known that in class D amplifier types, jitter within the clock used for PWM transitions shows up as output noise as it is. Arithmetic errors such as dropping lower bits in the digital processing of the PWM conversion contribute to output noise. In prior art class D amplifiers, as described in Japanese patent application Sho 59-183510, the output of the class D amplifier is filtered by a low pass filter so that it can be converted into the an...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03F3/217
CPCH03F3/38H03F1/26H03F3/217H03F2200/331
Inventor 森岛守人
Owner YAMAHA CORP