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Delay matching for clock distribution in a logic circuit

A technology of delay matching and clock distribution, applied in the directions of generating/distributing signals, electrical components, generating electrical pulses, etc., can solve the problem of propagation delay difference hindering the proper synchronization of frequency-divided clock signals and redistributed clock signals, destroying the proper operation of logic circuits, etc. question

Active Publication Date: 2010-05-26
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Propagation delay differences prevent proper synchronization of the divided and redistributed clock signals, disrupting proper operation of logic circuits

Method used

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  • Delay matching for clock distribution in a logic circuit
  • Delay matching for clock distribution in a logic circuit
  • Delay matching for clock distribution in a logic circuit

Examples

Experimental program
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Embodiment Construction

[0022] figure 1 is a block diagram illustrating the signal distribution circuit 10 . exist figure 1 In an embodiment of the present invention, circuit 10 receives clock signal CLK from clock source 11 and distributes the clock signal as well as a frequency-divided version of the clock signal within the logic circuit. The clock signal CLK can be, for example, a system clock or the output of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL).

[0023] A clock divider 12 divides the CLK signal into a lower frequency clock signal CLK / N and introduces a propagation delay d, eg, a clock-to-Q delay. The frequency-divided clock signal thus obtained is CLK / N+d. As will be described, clock divider circuit 12 may include a flip-flop that introduces a clock-to-Q delay in the divided clock signal CLK / N+d.

[0024] Delay matching circuit 14 resides within the redistribution path for original clock signal CLK. In larger logic circuits, the original clock signal CLK is re...

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Abstract

Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. Thedelay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

Description

technical field [0001] The present disclosure relates to compensation for propagation delay differences between clock signals distributed within logic circuits. Background technique [0002] Many devices include synchronous clock dividers to divide and redistribute clock signals within logic circuits. For example, high-speed telecommunications equipment uses different clock signals that are generated by dividing the original clock signal. In particular, a clock divider circuit reduces the frequency of the original clock signal. Ideally, the clock signals should be redistributed synchronously throughout the logic circuit such that the rising and falling edges of the original and divided clock signals are preferably aligned with each other. [0003] Unfortunately, the divided clock signal is typically delayed with respect to the original clock signal. In particular, the divided clock signal is sent from flip-flops utilizing the original clock signal. This flip-flop creates...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/04G06F1/10H03K3/037H03K5/135
CPCG06F1/10H03K3/0372G06F1/04H03K3/0375H03K5/135H03K3/00
Inventor 奥克塔维安·弗洛里斯卡
Owner QUALCOMM INC