Verifying system, establishing method of verifying system and verifying method

Abstract

This invention discloses a check system, a set-up method and a check method, in which, the check system includes a test excitation and drive module, a bus function model module corresponding to the bus set used in getting bus monitor signal of the set and pin information of clock reset pins and driving DUT by the converted test excited data, a clock and reset module for checking samples for generating clock sample signals and checking reset signals, a bus protocol monitor module corresponding to the bus set used in finishing exam to alternated protocols and getting bus data and envent signalscorresponding to the bus set, a chip functional level exam module for logic check.

Description

technical field [0001] The invention relates to the technical field of electronic testing, in particular to a system for verifying chip logic functions, and a method for creating a verification environment and a verification method. Background technique [0002] With the expansion of chip design scale, the workload of logic function verification is increasing, so how to improve the efficiency of logic verification and ensure its quality has become a relatively important issue. [0003] The traditional verification method is to verify the function of the chip module by engineers manually designing and generating the verification system of the module. This method is time-consuming and labor-intensive. Due to the difference in the ability of engineers, the quality of the verification system produced is uneven, and the verification quality is difficult to guarantee. Moreover, with the expansion of the chip scale and the increasingly complex functions, the complexity of the veri...

AI Technical Summary

Problems solved by technology

The chip contains a variety of modules, and each module has different functions. The manually generated module-level verification environment will also have some differences in structure due to different engineers. This will also cause some difficulties for the final system integration, resulting in more costs. The time and manpower in the maintenance of the verification environment will also have a bad impact on the verification quality

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