Semiconductor memory device using only single-channel transistor to apply voltage to selected word line

Abstract

A semiconductor memory device includes: a memory cell array in which memory cells are arranged in a matrix; and a row decoder circuit that selects a word line in the memory cell array and transmits a voltage to the word line. The row decoder circuit includes: a plurality of first transistors of the first conductivity type, one end of the current path of which is directly connected to each word line; a second transistor of the second conductivity type, and a pole of the first conductivity type. On the contrary, when the voltage is transmitted to the selected word line, the voltage is transmitted to the gate of the first transistor connected to the selected word line. The voltage transfer to the selected word line is performed only by the first transistor of the first conductivity type.

Description

[0001] This application is a divisional application of the invention patent application with the application number 01120869.4, the application date is June 8, 2001, and the invention title is "semiconductor storage device that only uses single-channel transistors to transmit voltage to selected word lines". technical field [0002] The present invention relates to a semiconductor storage device, and more specifically to a nonvolatile semiconductor storage device such as a NAND cell, a NOR cell, a DINOR cell, and an AND cell type EEPROM. Background technique [0003] Conventionally, an electrically rewritable EEPROM is known as a semiconductor memory device. What is striking is that the NAND cell type EEPROM, in which a plurality of memory cells are connected in series to form a NAND cell block, can be highly integrated. [0004] A memory cell, one of the NAND cell types EEPEOM, has a FET-MOS structure in which a floating gate (charge storage layer) and a control gate are la...

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Problems solved by technology

Therefore, there is a problem that the pattern area of ​​the row decoder circuit increases

[0025] In addition, in order to solve this problem, if the transistors connected to the word lines are provided as one per word line in the row decoder circuit, a pump circuit is required in the row decoder circuit, and since the pattern area of ​​the pump circuit increase, there is still the problem of increasing the graphic area of ​​the row decoder circuit

[0026] Furthermore, when the row decoder circuit is provided with one transistor connected to the word line per word line, and no pump circuit is provided in the row decoder circuit, it cannot be achieved without a voltage drop. Sending high voltage for writing to the word line increases the risk of insufficient data writing operation

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