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Control method for decoding MPEG2 video based on multiple pipeline control and optimizes buffer

A technology of MPEG-2 and control method, applied in the direction of digital video signal modification, TV, electrical components, etc., can solve the problem that data and status information cache cannot be optimally designed, etc.

Inactive Publication Date: 2006-12-06
XI AN JIAOTONG UNIV
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  • Application Information

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Problems solved by technology

However, due to the fact that separate data information and control information caches are generally used in decentralized control, and the characteristics of the global encoding state information and the decoding speed of the functional modules themselves are not utilized, the optimal design of the data and state information caches cannot be carried out (HuiWang, A Novel HDTV video decoder and decentralized control scheme, IEEETransactions on Consumer Electronics, November, 2001, the data and control information cache in the text uses 4Kb)

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  • Control method for decoding MPEG2 video based on multiple pipeline control and optimizes buffer
  • Control method for decoding MPEG2 video based on multiple pipeline control and optimizes buffer
  • Control method for decoding MPEG2 video based on multiple pipeline control and optimizes buffer

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Embodiment Construction

[0019] see figure 2 , the functional structure of the video decoder proposed by the present invention includes a macroblock basic block statistical module, a video code stream analysis (VSP) module, a sequence image register 1, 2, a variable length decoding (VLD) module, a frame memory, and an inverse Discrete cosine transform (IDCT) module, run-length decoding and inverse scanning (RLD / IZZ) module, macroblock level registers 1 and 2, EOB statistics module, MV_FIFO (MV cache), motion vector calculation (MV_C) module, motion compensation ( MC) module, and MS_FIFO, BS_FIFO, RL_FIFO.

[0020] The macro block basic block statistical module is connected with the video code stream analysis module (VSP) and the variable length decoding module (VLD) respectively, and the input and output of the video code stream analysis module (VSP) are also connected with MS_FIFO, sequence image registers 1 and 2, And connect with variable length decoding module (VLD) through BS_FIFO, variable len...

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Abstract

The method use a video stream processing module (VSP), a variable length decoding (VLD) module, a RLD module, an IZZ module, an IQ module and an IDCT module to construct macro pipeline architecture, and uses a functional module for buffering and matching MPEG-2 format data stream to control the decoding speed and the execution of decode pipeline in each functional module or to stop the buffered value and to adjust the macro block and image initial test signal; uses memory group having two memories to save control message variable. It can optimize the use of buffer while meeting the need of high speed and high performance decoding.

Description

technical field [0001] The invention belongs to the technical field of video decoding and VLSI design, is applied to ASIC design or software-hardware collaborative design of video decoding, and specifically relates to an MPEG-2 video decoding control method based on multi-pipeline control and cache optimization. Background technique [0002] The functional block diagram of MPEG-2 video decoding is as follows: figure 1 As shown, it mainly includes video stream analysis (VSP) module, variable length decoding (VLD) module, run length decoding and inverse scanning (RLD / IZZ) module, inverse quantization (IQ) module, inverse discrete cosine transform (IDCT) module , MV_C (motion vector calculation) and motion compensation (MC) and other functional module units. The MPEG-2 video decoder has high computational complexity and dense data flow and control flow. To optimize the whole system, it is necessary to use a reasonable control strategy to effectively schedul...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N7/30H04N7/50H04N19/44H04N19/91
Inventor 梅魁志郑南宁曾强周华锋胡丽娟张学臻赵晨
Owner XI AN JIAOTONG UNIV