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Realization process for synchronous channel transmitting code-level of broadband CDMA system

A wideband code division multiple access and synchronization channel technology, which is applied in the implementation field of the synchronization channel transmission chip-level processing, can solve the problems of low resource reuse rate and waste, and achieves improved integration, improved resource utilization, and increased availability. Effects of configuration flexibility

Active Publication Date: 2010-05-05
SANECHIPS TECH CO LTD
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The purpose of the present invention is to overcome the disadvantages of low resource reuse rate and waste caused by the low resource reuse rate and waste caused by the chip-level processing of synchronous channel transmission in the ASIC for transmitting the downlink physical channel of the baseband processor of the WCDMA system base station, and propose a synchronous channel transmission chip level implementation method, so that the synchronization channel transmission chip level processing can use other downlink physical channel transmission chip level processing resources to complete

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  • Realization process for synchronous channel transmitting code-level of broadband CDMA system
  • Realization process for synchronous channel transmitting code-level of broadband CDMA system

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Embodiment Construction

[0021] figure 1 The flow chart of chip-level processing for synchronous channel transmission provided by the present invention is given. The chip-level processing method for transmitting the synchronization channel provided by the present invention will be described in detail below in conjunction with this figure.

[0022] First obtain the main synchronization channel transmission sequence C pNew and Auxiliary Sync Channel to send sequence C sNew i，k : The main sync channel only sends ac in the first 256 chips of each slot p , implemented as a sequence C sent uniformly in every slot pNew , sequence C pNew The length is 2560 chips, and the value of the first 256 chips is ac p The 256 values ​​of the other chips are complex (0+0j); the auxiliary synchronization channel only sends ac in the first 256 chips of each slot s i，k , which is implemented as a sequence C evenly transmitted in the synchronous channel time slot with the time slot number k sNew i，k , sequence C s...

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Abstract

The invention relates to a method for sending code sheet in synchronous channel of wideband code division multiple access system, which comprises: obtaining the main synchronous channel sending sequence CpNew and the auxiliary synchronous channel sending sequence CsNewi, k; then completing the projections of main synchronous channel sending sequence CpNew and the auxiliary synchronous channel sending sequence CsNewi, k; based on other treatments of descending physical channel, completing the frequency expansion, interference and weighting on the synchronous channel. With said invention, the resource used in other descending physical channel sending code treatment can be used to send code of synchronous channel, to improve the resource utilization and integration of base band processor of WCDMA system and reduce the cost of single channel.

Description

technical field [0001] The invention relates to the field of baseband processors of wideband code division multiple access (WCDMA) base stations, in particular to a method for realizing synchronous channel transmission chip-level processing. Background technique [0002] The synchronization channel is a downlink physical channel necessary to support cell search in a wideband code division multiple access system, and includes two sub-channels: a primary synchronization channel (P-SCH) and a secondary synchronization channel (S-SCH). The third generation partnership (3GPP) stipulates that the transmission frame structure of the synchronization channel is 10 milliseconds per frame, each frame includes 15 time slots, each time slot is 2560 chips (chip), and the chip rate is 3.84 MHz. Each time slot number in a frame starts from the first time slot number 0, and each time slot number is 1 greater than the previous time slot number, until the last time slot number is 14. 3GPP spec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J13/02H04B1/7073H04L25/02
Inventor 赵延宾陈月峰徐心明刘新阳
Owner SANECHIPS TECH CO LTD