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Field-programmable gate array configuration circuit, radio-frequency unit and magnetic resonance system

a field-programmable gate array and configuration circuit technology, applied in the field of electronic elements, can solve the problem that the fpga architecture cannot achieve configuration, and achieve the effect of improving system security

Active Publication Date: 2019-08-20
SIEMENS HEALTHCARE GMBH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

Enhances configuration flexibility and system security by allowing the FPGA architecture to read and use configuration files from alternative storage devices in case of failures, ensuring continued operation even if one storage device is faulty.

Problems solved by technology

Moreover, if a fault occurs in the storage device storing a configuration file in the form of firmware and a configuration file in the form of loadware in a centralized manner, the master FPGA module will be unable to read any configuration file, with the result that the FPGA architecture will be unable to accomplish configuration.

Method used

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  • Field-programmable gate array configuration circuit, radio-frequency unit and magnetic resonance system
  • Field-programmable gate array configuration circuit, radio-frequency unit and magnetic resonance system
  • Field-programmable gate array configuration circuit, radio-frequency unit and magnetic resonance system

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0034]As noted above, FIG. 1 is a structural diagram of an FPGA configuration circuit according to the present invention.

[0035]As FIG. 1 shows, the configuration circuit 100 has:[0036]n (n being a natural number of at least 2) FPGA modules 51, 52 . . . 5n which are individually connected to a bus 3;[0037]a first storage device 1, storing a configuration file 11 in the form of firmware;[0038]a second storage device 2, storing a configuration file 21 in the form of loadware;[0039]one of the n FPGA modules (e.g. FPGA module 5n) being connected to the first storage device 1 and the second storage device 2 separately, the FPGA module 5n being a master FPGA module, while the other FPGA modules are slave FPGA modules;[0040]an input end 4, connected to the first storage device 1 and the second storage device 2 separately, and providing a selection signal for selecting one of the first storage device 1 and the second storage device 2;[0041]wherein the FPGA module 5n connected to the first st...

second embodiment

[0050]As noted above, FIG. 2 is a structural diagram of an FPGA configuration circuit according to the present invention.

[0051]As FIG. 2 shows, the configuration circuit 200 has:[0052]n (n being a natural number of at least 2) FPGA modules 51, 52 . . . 5n which are individually connected to a bus 3;[0053]a first storage device 1, storing a configuration file 12 in the form of firmware, a version number of the configuration file being 1;[0054]a second storage device 2, storing a configuration file 22 in the form of firmware, a version number of the configuration file being 2;[0055]one of the n FPGA modules (e.g. FPGA module 5n) being connected to the first storage device 1 and the second storage device 2 separately, the FPGA module 5n being a master FPGA module, while the other FPGA modules are slave FPGA modules;[0056]an input end 4, connected to the first storage device 1 and the second storage device 2 separately, and providing a selection signal for selecting one of the first sto...

third embodiment

[0065]As noted above, FIG. 3 is a structural diagram of an FPGA configuration circuit according to the present invention.

[0066]As FIG. 3 shows, the configuration circuit 300 has:[0067]n (n being a natural number of at least 2) FPGA modules 51, 52 . . . 5n which are individually connected to a bus 3;[0068]a first storage device 1, storing a configuration file 13 in the form of loadware, a version number of the configuration file being 1;[0069]a second storage device 2, storing a configuration file 23 in the form of loadware, a version number of the configuration file being 2;[0070]one of the n FPGA modules (e.g. FPGA module 5n) being connected to the first storage device 1 and the second storage device 2 separately, the FPGA module 5n being a master FPGA module, while the other FPGA modules are slave FPGA modules;[0071]an input end 4, connected to the first storage device 1 and the second storage device 2 separately, and providing a selection signal for selecting one of the first sto...

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Abstract

In a field-programmable gate array (FPGA) configuration circuit, and a radio-frequency unit and a magnetic resonance system having a configuration circuit, the configuration circuit has at least two FPGA modules, each FPGA module being individually connected to a bus; at least two storage devices, each storage device storing a configuration file; one of the at least two FPGA modules being connected to the at least two storage devices separately, and an input end, connected separately to the at least two storage devices. A selection signal is provided for selecting one of the at least two storage devices. The FPGA module connected to the at least two storage devices reads a configuration file stored in a storage device selected on the basis of the selection signal, and sends, via the bus, the configuration file that has been read to the FPGA module other than the FPGA module connected to the at least two storage devices.

Description

BACKGROUND OF THE INVENTION[0001]Field of the Invention[0002]The present invention concerns the technical field of electronic elements, in particular to a field-programmable gate array (FPGA) configuration circuit, a radio-frequency unit and a magnetic resonance system.[0003]Description of the Prior Art[0004]A field-programmable gate array (FPGA) is a programmable device. Unlike conventional logic circuits and gate arrays, an FGPA utilizes small lookup tables to realize combinational logic. Each lookup table is connected to an input end of a D flip-flop. The D flip-flop drives another logic circuit or drives an I / O, thereby forming a basic logic unit module capable of realizing a combinational logic function as well as a sequential logic function.[0005]Master-slave mode FPGA architectures are quite common at present. In a master-slave mode FPGA architecture, a master FPGA module is responsible for reading a configuration file from a storage device, and based on the configuration fil...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06F13/12G06F13/42G06F15/78G06F9/44
CPCG06F13/4265G06F15/7871G06F9/44
Inventor XIE, SHU QUNYU, HAI BOZHU, WEN BIN
Owner SIEMENS HEALTHCARE GMBH