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Clock control method and circuit

a control method and clock technology, applied in the direction of generating/distributing signals, pulse techniques, instruments, etc., can solve the problems of long time period of time on the order of several hundred to several thousand cycles, circuits tend to degrade synchronization characteristics, prolonging lock time, etc., and achieve the effect of reducing jitter

Inactive Publication Date: 2001-11-15
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The solution effectively reduces clock signal jitter without relying on feedback circuits like PLLs, enhances jitter suppression by connecting timing averaging circuits in series, and supports high-frequency clocks using multiphase signals, while maintaining synchronization and reducing external jitter influence.

Problems solved by technology

However, these clock control circuits can be a source of clock jitter and are susceptible to jitter of the system clock, in which case locking time is prolonged.
Thus, these circuits tend to degrade the synchronization characteristic.
Because a PLL is a feedback circuit, however, a long period of time on the order of several hundred to several thousand cycles is required until the clock stabilizes.
In addition, if jitter is too large, there is the possibility that the PLL will not remain locked.
A problem that arises, therefore, is that external clock jitter passes through the delay circuit as is and is transmitted to the internal circuitry from a clock driver 106.

Method used

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  • Clock control method and circuit
  • Clock control method and circuit
  • Clock control method and circuit

Examples

Experimental program
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Effect test

embodiment 1-1

[0115] [Embodiment 1-1]

[0116] FIG. 3 is a diagram useful in describing a first embodiment of the present invention. According to this embodiment, averaging of the timing of a clock signal is performed using a 2-phase clock. To accomplish this, a frequency divider (a divide-by-two divider) 300 for generating a 2-phase clock is disposed in forestage of timing averaging circuits 301, 302. In order to average the timings of the edges of the 2-phase clock, the timing averaging circuit 301 is composed of timing dividing circuits 304-1, 304-2 arranged in parallel in a number equal to the number of clock phases. Similarly, the timing averaging circuit 302 is constituted by timing dividing circuits 304-3, 304-4 arranged in parallel. The outputs of the timing dividing circuits 304-1, 304-2 are input to the timing dividing circuits 304-3, 304-4, which proceed to output signals representing the averaged timings of these input signals. The outputs of the timing dividing circuits 304-3, 304-4 of ...

embodiment 1-2

[0125] [Embodiment 1-2]

[0126] FIG. 6 is a diagram illustrating an example of the construction of the timing dividing circuit (TMD) according to a second embodiment of the present invention. Since a 2-phase clock is used as the clock signal, timing division is performed using complementary signals. With this timing dividing circuit, therefore, three intervals are required, namely a first interval over which charging is performed by one of the PMOS transistors MP1, MP2, a second interval over which charging is performed by both PMOS transistors MP1 and MP2, and a third interval over which the accumulated charge is discharged.

[0127] To accomplish this, as shown in FIG. 6, the output IN1.IN1d.NAND of a NAND gate whose inputs are the signal IN1 and a signal IN1d obtained by delaying the signal IN1 by a delay element DL1 is connected (fed) to the gate of the PMOS transistor MP2, which forms a switch for charging the capacitor C; and the output IN1.IN2d.NOR (the period of the signals IN1, ...

embodiment 1-3

[0128] [Embodiment 1-3]

[0129] A third embodiment will be described with reference to FIGS. 8 and 9. Averaging of timing is performed in this embodiment using a 4-phase clock. To accomplish this, a frequency divider 603 for generating a 4-phase clock is disposed in forestage of timing averaging circuits 601, 602. In order to average the timings of the edges of the 4-phase clock, the timing averaging circuit is composed of timing dividing circuits TMD 701-1 to 701-4 arranged in parallel in a number equal to the number of clock phases, as shown in FIG. 9. NAND gates NAND1 to NAND4 each output a one-shot pulse based upon every two outputs from among the outputs produced by the timing dividing circuits TMD 701-1 to 701-4, and outputs of pairs of the NAND gates NAND1 to NAND4 are combined by NAND gates NAND5 to NAND8, whereby a 4-phase clock of reduced jitter is produced.

[0130] Though the number of clock phases increases with this embodiment, the fact that a 4-phase clock is used makes it...

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PUM

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Abstract

A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.

Description

STATUS OF RELATED APPLICATIONS[0001] The entire disclosure of the copending U.S. patent application Ser. No. 09 / 087,864 filed on Jun. 1, 1998 by the same applicant as the present application is incorporated herein by reference.[0002] This invention relates to a method of controlling clock signals and to a clock control circuit. More particularly, the invention relates to a clock signal control method and circuit ideal for application to a semiconductor integrated circuit device synchronized to a system clock to control internal circuitry. More specifically, the invention relates to a circuit that uses a timing averaging circuit for clock control, as well as to a clock control circuit that uses a timing averaging circuit in a synchronizing circuit such as a delay-locked loop, phase synchronizing loop or synchronous delay circuit.DESCRIPTION OF THE RELATED ART[0003] In a semiconductor integrated circuit synchronized to a system clock to control internal circuitry, the entirety of the ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F1/10G11C11/407G11C11/4076H03H11/26H03K5/13H03K5/135H03L7/00H04L7/00H04L7/033
CPCG06F1/10H03K5/133H03K5/135H03K2005/00052
Inventor SAEKI, TAKANORI
Owner RENESAS ELECTRONICS CORP