Partitionable embedded circuit test system for integrated circuit

Abstract

A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.

Description

[0001] This application claims benefit of Provisional Application No. 60 / 160,233 filed Oct. 18, 1999. The entire disclosure of Provisional Application No. 60 / 160,233 is hereby incorporated by reference herein.[0002] 1. Field of the Invention[0003] The present invention relates in general to a system for testing circuits embedded in an integrated circuit (IC), and in particular to a system that may be flexibly partitioned between components internal and external to the IC.[0004] 2. Description of Related Art[0005] Many integrated circuits (ICs) include one or more embedded circuits such as random access memories (RAMs). While logic circuits implemented in an IC itself may read or write access an embedded RAM, the bus conveying data, address and control signals between the RAM and the logic circuits read and write accessing it may not be accessible to external test equipment via the IC's input / output (I / O) terminals. Conventional IC testers external to the IC therefore can't directly ...

AI Technical Summary

Benefits of technology

0028] It is another object of the invention to provide a test system allowing an IC designer to flexibly select a manner in which each RAM is tested and to flexibly apportion test functions between test circuits internal and external to the IC.

Problems solved by technology

While logic circuits implemented in an IC itself may read or write access an embedded RAM, the bus conveying data, address and control signals between the RAM and the logic circuits read and write accessing it may not be accessible to external test equipment via the IC's input / output (I / O) terminals.

Conventional IC testers external to the IC therefore can't directly test such an embedded RAM.

However this approach requires a large number of extra I / O terminals to accommodate the RAM's I / O ports and can require a substantial amount of scarce space within the IC to route large buses between each embedded RAM and the IC's I / O terminals.

This approach can eliminate the need for extra I / O terminals, but can still require substantial amounts of IC space for routing the large embedded memory buses.

But this approach requires routing large buses within the IC for connecting a central BIST circuit to each embedded RAM, and those buses can require substantial space in the IC.

It not possible to use a single BIST circuit for testing multiple embedded RAMs when the embedded RAMs have differing address ranges or are to be tested in different ways.

Since IC designers must custom design a test system for each IC to suit the nature of its embedded RAMs, they find BIST systems difficult to implement.

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