Method and apparatus for operating a non-volatile memory array

Abstract

A string of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of the selected memory cell. The charge storage state of the charge trapping structure affects the measured current.

Description

RELATED APPLICATIONS [0001] This application is related to co-pending U.S. application Ser. No. 10 / ______, filed on the same date as the present application entitled METHOD AND APPARATUS FOR OPERATING A NON-VOLATILE MEMORY DEVICE, and to co-pending U.S. application Ser. No. 10 / ______, filed on the same date as the present application entitled METHOD AND APPARATUS FOR OPERATING A NON-VOLATILE MEMORY ARRAY.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to electrically programmable and erasable non-volatile memory, and more particularly to charge trapping memory that reads the contents of the charge trapping structure of the memory cell with great sensitivity. [0004] 2. Description of Related Art [0005] Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EE...

AI Technical Summary

Benefits of technology

[0013] In some embodiments, the body region is a well in a semiconductor substrate. In other embodiments, the body region is simply the semiconductor substrate.

[0014] In some embodiments, the logic applies a second bias arrangement to adjust the charge storage state by increasing a net positive charge in the charge trapping structure, and applies a third bias arrangement to adjust the charge storage state by increasing a net negative charge in the charge trapping structure. In some embodiments, the second bias arrangement corresponds to programming and the third bias arrangement corresponds to erasing, and in other embodiments the second bias arrangement corresponds to erasing and the third bias arrangement correspond to programming. As generally used herein, programming refers to adding limited amounts of charge in the charge trapping structure, such as by the addition of holes or electrons to the charge trapping structure. Also as generally used herein, erasing refers to resetting the charge storage state of the charge trapping structure, such as by adding a single charge type throughout the charge trapping structure until equilibrium is reached. The invention encompasses bot

Problems solved by technology

However, the first voltage difference and the second voltage differences fail to change the charge storage state.

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