Etching method and method for forming contact opening

a contact opening and etching technology, applied in the field of etching methods, can solve the problems of increasing the difficulty and cost of high-resolution lithography techniques, the inability of the corresponding opening in the etching layer to meet the requirements, and the dimension of the semiconductor device unceasingly getting smaller, so as to reduce the after-etching inspection. effect of inspection

Active Publication Date: 2006-12-14
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0006] In view of the foregoing, this invention provides an etching...

Problems solved by technology

As the integration degree of IC is always required to be higher, the dimension of semiconductor devices unceasingly gets smaller.
However, high-resolution lithography techniques are more difficult and expensive due to the limitations of optics.
However, since an opening in the photoresist layer and the anti-reflection coating (ARC) is easily expanded in such an etching method, the CD of the corres...

Method used

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  • Etching method and method for forming contact opening
  • Etching method and method for forming contact opening
  • Etching method and method for forming contact opening

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Embodiment Construction

[0027] Referring to FIG. 1A, a semiconductor substrate 100 having a metal-oxide-semiconductor (MOS) device thereon is provided, wherein the MOS device is isolated from adjacent devices by an isolation structure 110 like a shallow-trench-isolation (STI) structure. In the MOS device, a gate 104 is formed on a gate dielectric layer 102, and a spacer 106 is formed on the sidewall of the gate 104. A source region 108 and a drain region 110 are formed in the substrate 100 beside the gate 104. In another embodiment, a metal suicide layer 112 is further formed on the gate 104, the source region 108 and the drain region 110 to reduce their resistance, wherein the material of the metal silicide layer 112 may be nickel silicide, tungsten silicide or cobalt silicide, etc. Because the material and forming method of each part in the above MOS device are known to one of ordinary skills, the description of them is omitted here.

[0028] Referring to FIG. 1B, a dielectric layer 115 is formed on the su...

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Abstract

An etching method is described, including a first etching step and a second etching step. The temperature of the second etching step is higher than that of the first etching step, such that the after-etching-inspection (AEI) critical dimension is smaller than the after-development-inspection (ADI) critical dimension.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to an etching method. More particularly, the present invention relates to an etching method capable of reducing critical dimension (CD), and to a method for forming a contact opening that utilizes the etching method. [0003] 2. Description of the Related Art [0004] As the integration degree of IC is always required to be higher, the dimension of semiconductor devices unceasingly gets smaller. In the prior art, the miniaturization of pattern pitch in IC fabrication is mostly made by enhancing the lithographic resolution. However, high-resolution lithography techniques are more difficult and expensive due to the limitations of optics. [0005] Instead of enhancing lithographic resolution, the critical dimension of pattern after etching can be reduced alternatively by modifying the etching process. In the modified etching method, a patterned photoresist layer with an after-development-inspect...

Claims

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Application Information

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IPC IPC(8): H01L21/302
CPCH01L21/31116H01L21/31144H01L21/76834H01L21/76816H01L21/32135
Inventor CHOU, PEI-YULIAO, JIUNN-HSIUNG
Owner UNITED MICROELECTRONICS CORP
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