Memory Device Having a Delay Locked Loop and Multiple Power Modes

Abstract

A single chip dynamic random access memory has a memory core, including dynamic random access memory cells, and a clock receiver circuit to receive an external clock signal. A delay locked loop circuit is coupled to the clock receiver circuit. In a first power mode, the delay locked loop circuit and the clock receiver circuit are turned on. Power consumption in the first power mode is less than that consumed while in an active mode. In a second power mode, the delay locked loop circuit is turned off. The memory is configured to receive a command that specifies a power down mode, to turn off the delay locked loop circuit in response to the command that specifies the power down mode, and to operate the memory device in a standby power mode. The delay locked loop circuit and the clock receiver circuit are turned on in a standby mode.

Description

RELATED APPLICATIONS [0001] This application is a continuation of U.S. application Ser. No. 10 / 742,327 filed Dec. 18, 2003, which is a continuation of U.S. application Ser. No. 09 / 887,181 filed Jun. 21, 2001, now U.S. Pat. No. 6,701,446, which is a continuation of U.S. application Ser. No. 09 / 169,378 filed Oct. 9, 1998, now U.S. Pat. No. 6,263,448, which claims the benefit of U.S. Provisional Application No. 60 / 061,664 filed Oct. 10, 1997. [0002] This application is a related to U.S. application Ser. No. 11 / 107,504, filed Apr. 15, 2005, entitled “Memory Device Having a Read Pipeline and a Delay Locked Loop,” which application is incorporated herein by reference. [0003] A related application was filed on May 7, 1996, U.S. application Ser. No. 08 / 648,300, entitled “Asynchronous Request / Synchronous Data Dynamic Random Access Memory”, assigned to the same assignee as this application, now U.S. Pat. No. 6,209,071, hereby incorporated by reference as background information.BACKGROUND OF T...

AI Technical Summary

Benefits of technology

[0012] In one embodiment, the present invention separates out the RAS control logic into a separate clock domain from the CAS control logic. This smaller amount of RAS control logic can then be left on in a standby power mode to eliminate any visible latency from a RAS signal through to data access.

Problems solved by technology

Power consumption is a constraint on computer systems both by virtue of limited power available in portable, battery-operated systems, and also limited heat dissipation for high power devices.

As devices are made faster by increasing their clock speed, the power requirements also increase since clock signal lines, receivers, and other clock circuits consume more power and generate more heat as device clock rates increase.

For these synchronous systems, clock power becomes an important issue at high frequencies.

High power consumption by the clock signal can exceed thermal cooling limits of the package or system or cause excessive battery drain in portable devices.

One disadvantage of the prior Rambus system is the additional latency required for turning on the control logic to exit the standby power mode.

Since the interface control logic and datapath are turned on before an incoming command is processed and a memory operation started, the turn-on latency of the control logic and datapath directly adds to the memory access latency.

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