Novel context instruction cache architecture for a digital signal processor

Abstract

Improved thrashing aware and self configuring cache architectures that reduce cache thrashing without increasing cache size or degrading cache hit access time, for a DSP. In one example embodiment, that is accomplished by selectively caching only the instructions having a higher probability of recurrence to considerably reduce cache thrashing.

Description

TECHNICAL FIELD OF THE INVENTION[0001]The present invention relates to digital signal processors, and more particularly to real-time memory management for digital signal processors.BACKGROUND OF THE INVENTION[0002]A digital signal computer or digital signal processor (DSP) is a special purpose computer that is designed to optimize performance for digital signal processing applications, such as, for example, fast Fourier transforms, digital filters, image processing and speech recognition. DSP applications are characterized by real-time operation, high interrupt rates, and intensive numeric computations. In addition, DSP applications tend to be intensive in memory access operations and to require the input and output of large quantities of data. Thus, designs of DSPs may be quite different from those of general purpose processors.[0003]One approach that has been used in the architecture of DSPs is the Harvard architecture, which utilizes separate, independent program and data memorie...

AI Technical Summary

Benefits of technology

[0007]According to an aspect of the subject matter, there is provided a method for reducing cache thrashing in a DSP, comprising the steps of dynamically enabling caching of instructions upon encountering current frequently executed instructions in a program, and dynamically disabling the caching of the instructions upon encountering an exit point associated with the frequently executed instructions.

Problems solved by technology

DSP applications are characterized by real-time operation, high interrupt rates, and intensive numeric computations.

In addition, DSP applications tend to be intensive in memory access operations and to require the input and output of large quantities of data.

Thus, designs of DSPs may be quite different from those of general purpose processors.

When instructions and data are stored in the program memory, conflicts may arise in the fetching of instructions.

Further, in the case of Harvard architecture, the instruction fetch and the data access can take place in the same clock cycle, which can lead to a conflict on the program memory bus.

In this scenario, instructions which can generally be fetched in a single clock cycle for a case can stall a cycle due to conflict.

Most of the cache architectures suffer from performance degradation due to cache thrashing, i.e., loading the cache with instruction and then removing it while it is still needed before it can be used by the computer system.

Cache thrashing is, of course, undesirable, as it reduces the performance gains.

However, these techniques come with overheads like extra hardware, increased cache hit access time, and / or higher software overhead.

However, this technique requires additional overheads in terms of requiring profiling of code by user and extra instructions in the code to lock the cache.

Further, this can make the code very cumbersome.

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