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Semiconductor device and method for manufacturing a semiconductor device

a semiconductor and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device details, electrical equipment, etc., can solve the problem of inability to arrange the large number of conducting lines in the layer

Inactive Publication Date: 2009-07-02
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes a semiconductor device that includes a semiconductor chip with conducting elements and a layer of conducting elements located adjacent to the chip. The chip is connected to the layer of conducting elements through contact elements. The device also includes a fourth conducting element that crosses the first conducting element in a vertical projection. The technical effect of this design is that it allows for more efficient and reliable electrical connection between the chip and the layer of conducting elements. Additionally, the method of manufacturing the device allows for the separation of the chips after the application of a metallization layer, which improves the overall quality of the device.

Problems solved by technology

Especially with high pin counts, the problem frequently occurs that the high number of conducting lines in the layer cannot be arranged without crossings between at least some of the lines.
In a single metallization layer, a crossing of two lines can not be realized because this would cause an electrical shortcut between the lines.

Method used

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  • Semiconductor device and method for manufacturing a semiconductor device
  • Semiconductor device and method for manufacturing a semiconductor device
  • Semiconductor device and method for manufacturing a semiconductor device

Examples

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Embodiment Construction

[0019]Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only.

[0020]The term “connected” is used in this context for a direct connection of two elements, which includes that the elements are electrically connected. The term “electrically connected” means that two elements are in electrical contact, but can be connected over an intermediate element, hence they need not be directly con...

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PUM

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Abstract

A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a second location, and a fourth conducting element arranged outside the semiconductor chip. A vertical projection of the fourth conducting element on the chip crosses the first conducting element between the first location and the second location.

Description

[0001]This invention refers to embodiments of semiconductor devices and methods for their production, particularly the electrical connection between a semiconductor chip and its supporting structure.BACKGROUND[0002]In the production of semiconductor devices, small contact elements on the semiconductor chip have to be connected to electrical terminals which provide a contact to the outside world. These connections are generally realized as part of the package or encapsulation of the semiconductor chip, e.g. by providing a metallization layer on a face of the chip which provides conducting elements or lines connecting the contact elements of the chip to contact elements on an outer face of the package, e.g. solder balls. Especially with high pin counts, the problem frequently occurs that the high number of conducting lines in the layer cannot be arranged without crossings between at least some of the lines. In a single metallization layer, a crossing of two lines can not be realized b...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/485
CPCH01L21/6835H01L2224/16235H01L23/5389H01L24/96H01L2224/04105H01L2224/16H01L2224/20H01L2224/92H01L2924/01013H01L2924/01029H01L2924/15174H01L2924/15311H01L2924/19042H01L23/48H01L2224/0401H01L24/19H01L2924/01005H01L2924/01068H01L2924/014H01L2224/96H01L2224/82H01L21/568H01L2224/12105H01L2924/181H01L2224/16227H01L2924/19015H01L2924/19104H01L2924/00H01L23/5381H01L2224/02H01L23/12H01L23/50H01L24/06H01L24/14H01L2924/15312H01L2924/15313
Inventor KUTTER, CHRISTOPHSOUTSCHEK, EWALDMEYER-BERG, GEORG
Owner INTEL CORP