Method for Accounting for Process Variation in the Design of Integrated Circuits

Abstract

A method to simulate an electronic circuit includes determining process parameters and a process variation for each process parameter, and determining a value for each of a plurality of components of the circuit as a function of the process variations.

Description

BACKGROUND OF THE INVENTION[0001]During the process of making semiconductor chips, each manufactured semiconductor chip is a little bit different because of process variations. Designers need to create as many chips as possible that work in spite of these process variations. Process variations are a function of many variables, and the width, thickness, and inter-layer thickness can vary independently for each layer on a chip, as can temperature and voltage. Currently designers cope with these variations by designing circuits using traditional methods such as picking a few subsets of variations, called process corners, and analyzing performance at these corners. However, these approaches are both too conservative (the specified conditions will seldom occur) and not conservative enough (they miss errors that can occur due to process variation).[0002]For example, building a chip is a sequence of hundreds of operations, each of which will occur a little differently on each chip despite ...

AI Technical Summary

Benefits of technology

This approach provides less pessimistic timing numbers and enables yield optimization by considering inter-chip and intra-chip variations, reducing the likelihood of missed errors and improving chip design efficiency.

Problems solved by technology

However, these approaches are both too conservative (the specified conditions will seldom occur) and not conservative enough (they miss errors that can occur due to process variation).

First, there is variation from chip to chip, for example, often the logic on one chip is significantly faster than on another chip.

Since working in 30 or so dimensions is difficult, designers have made various approximations.

However, this approach does not address intra-chip variation at all, as it assumes all nets and cells scale exactly the same way.

Intra-chip variations, which are smaller than inter-chip variation, but are still present in a chip, are difficult to consider using traditional approaches.

The major worry is that problems may arise if the clock and data signals do not track precisely.

This is not a serious restriction if the clock network is built from the ground up, but is hard to enforce in an era of discrete electronic blocks, each with their own clocking structure.

One big problem with worst case analysis is that it is too conservative.

Without further analysis, however, we cannot tighten this bound, however, since it is possible that at least some critical paths axe determined by only one process dimension (say metal-1 resistance).

The other problem is that corner analysis is not conservative enough, or in other words it can miss real errors.

OPC (Optical Proximity Correction) tries to correct this, but will not succeed completely.

Metal fill will try to fix this, but will also not succeed completely.

However, if a block is extracted in isolation, the average local metal density is not known for features near the sides or corners.

Traditional approaches also require multiple runs of extraction and timing analysis to catch both the errors due to signals that are too fast and the errors due to signals that are too slow.

Yet another problem is that since existing methods consider only one process point, either a net is critical or it is not.

There is no way to know how much the improvement of a non-critical net is worth using existing methods.

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