Methods for statistical slew propagation during block-based statistical static timing analysis
a statistical static timing and block-based technology, applied in the field of integrated circuit design, can solve the problems of significant errors, overly optimistic and misleading optimization tools, and the delay sensitivity to slew can be highly non-linear
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[0021]With reference to FIG. 1, a process flow 10 for a statistical timer that performs statistical static timing analysis (SSTA) is shown. The statistical timer utilizes a block-based approach to SSTA that propagates probability distribution functions, or an approximation thereof, from each node to the successive node and, so on, until each probability distribution function reaches a sink node. The probability distribution functions are propagated using a statistical maximum operation for early mode ATs (setup timing constraint) or a statistical minimum operation for late mode ATs (hold timing constraint).
[0022]In block 12, inputs are supplied to the statistical timer. Specifically, the statistical timer reads and flattens a netlist representing the structure of the circuit to be analyzed, a set of timing assertions, a set of canonical delay models governing the sources of variation in the space of process variations, sensitivities relating the delay attributable to each individual...
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