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Methods for statistical slew propagation during block-based statistical static timing analysis

a statistical static timing and block-based technology, applied in the field of integrated circuit design, can solve the problems of significant errors, overly optimistic and misleading optimization tools, and the delay sensitivity to slew can be highly non-linear

Active Publication Date: 2009-11-19
SIEMENS PROD LIFECYCLE MANAGEMENT SOFTWARE INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0018]By performing these slew perturbations, the second order effect that input slew has on delay and output slew is implicitly included in the sensitivity calculation for the delay and the output slew. Alternatively, after the output slew sensitivity for each of the parameters is calculated, data collected from these per-parameter slew perturbations may be used to explicitly calculate second order finite difference calculations. For any particular parameter upon which the input slew is sensitive and the delay and / or output slew is not sensitive, additional perturbations of the input slew may be required in order to account for the pure second order effects in the delay and the output slew.

Problems solved by technology

Even then, the results may be overly pessimistic and misleading for optimization tools.
A test run that passes in a single process corner under in a DSTA timing run may actually fail without detection in one or more other performance-limiting corners in the process space, which a SSTA timing run would reveal.
A problem with the use of a single sensitivity value dD / dSlew in the calculation of the delay is that the dependence of the delay on input slew may vary significantly across the parameter space, which may lead to significant errors.
In particular, the delay sensitivity to slew can be highly non-linear as a function of process corner.

Method used

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  • Methods for statistical slew propagation during block-based statistical static timing analysis
  • Methods for statistical slew propagation during block-based statistical static timing analysis
  • Methods for statistical slew propagation during block-based statistical static timing analysis

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Embodiment Construction

[0021]With reference to FIG. 1, a process flow 10 for a statistical timer that performs statistical static timing analysis (SSTA) is shown. The statistical timer utilizes a block-based approach to SSTA that propagates probability distribution functions, or an approximation thereof, from each node to the successive node and, so on, until each probability distribution function reaches a sink node. The probability distribution functions are propagated using a statistical maximum operation for early mode ATs (setup timing constraint) or a statistical minimum operation for late mode ATs (hold timing constraint).

[0022]In block 12, inputs are supplied to the statistical timer. Specifically, the statistical timer reads and flattens a netlist representing the structure of the circuit to be analyzed, a set of timing assertions, a set of canonical delay models governing the sources of variation in the space of process variations, sensitivities relating the delay attributable to each individual...

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Abstract

Methods for statistical slew propagation in static statistical timing analysis. The method includes projecting a canonical approximation of an input slew over a timing path to a first corner and using the projected input slew to calculate a delay and an output slew at the first corner. The method further includes perturbing the canonical approximation of the input slew to a different corner, calculating a delay and an output slew at the different corner using the perturbed input slew canonical, and determining a sensitivity of the delay and the output slew to a plurality of parameters, simultaneous with implicit sensitivity calculations to the input slew, with finite difference calculations between the first corner and perturbed data.

Description

FIELD OF THE INVENTION[0001]The invention relates generally to integrated circuit design and, in particular, to statistical static timing analysis for analyzing the timing characteristics of an integrated circuit, before physically fabricating the integrated circuit.BACKGROUND OF THE INVENTION[0002]Static timing analysis (STA) is used to compute the expected timing of a digital circuit to identify problem areas of an integrated circuit during the design phase and in advance of actual fabrication. Timing runs in STA simulate the timing of the integrated circuit to determine whether or not the integrated circuit meets various timing constraints and, therefore, is likely to operate properly if fabricated in accordance with the tested design.[0003]Deterministic static timing analysis (DSTA) propagates timing quantities, such as arrival times (ATs), required arrival times (RATs), and slews, along with any other timing related quantities (guard times, adjusts, asserts, etc.), in a timing ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F17/50
CPCG06F2217/84G06F17/5031G06F30/3312G06F2119/12
Inventor HEMMETT, JEFFREY G.VISWESWARIAH, CHANDRAMOULIZOLOTOV, VLADIMIR
Owner SIEMENS PROD LIFECYCLE MANAGEMENT SOFTWARE INC
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