Circuit reliability analysis method

An analysis method and reliability technology, applied in CAD circuit design, electrical digital data processing, instruments, etc., can solve the problems of difficult to support statistical static timing analysis, difficult to support fluctuation and aging analysis, high complexity, and achieve statistical Static timing analysis, accelerated application, accurate simulation results

Active Publication Date: 2020-11-06
PEKING UNIV
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  • Abstract
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  • Claims
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Problems solved by technology

[0006] It can be seen that the existing circuit reliability simulation technology is difficult to support fluctuation and aging analysis, it is difficult to support statistical static timing analysis (statistical static timing analysis), and the accuracy is low and the complexity is high

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Embodiment Construction

[0024] Below in conjunction with accompanying drawing, further describe the present invention through embodiment, but do not limit the scope of the present invention in any way.

[0025] The invention provides a path-based circuit reliability analysis method, which does not need to establish a degradation-aware standard cell library, and can also support statistical static timing analysis. figure 1 Shown is the flow process of the inventive method, and concrete implementation comprises the steps:

[0026] Step 1. Select a representative path:

[0027] In order to realize path-based analysis, the present invention proposes a new representative path selection method. Although the degradation speed of different paths is different, it is impossible for a path with too small initial delay to become a critical path. First, perform static timing analysis, and then filter out short paths whose initial delay is less than 90% of the initial critical path delay (the longest path delay ...

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Abstract

The invention discloses a circuit reliability analysis method, which relates to an integrated circuit reliability design technology, and comprises the following steps of: firstly, synthesizing a circuit, performing path analysis and calculating a workload, and obtaining an input condition, a load condition and a degradation degree of each logic gate on a critical path; and then transistor-level Monte Carlo simulation is carried out, transistor-level simulation degradation information is utilized, and a circuit degradation perception standard cell library does not need to be established, so that a simulation result is more accurate, application of nodes in a circuit is accelerated, and statistical static timing analysis is supported.

Description

technical field [0001] The invention relates to integrated circuit reliability design technology, in particular to a circuit reliability analysis method. Background technique [0002] As microelectronics processes continue to scale down, reliability issues are getting worse. Under advanced technology nodes, process variation and device aging bring greater uncertainty to the service life of the circuit, making the design margin of the circuit smaller and smaller. In order to meet the service life requirements of the circuit, a larger frequency / voltage guardband (guardband) needs to be added to the design, which will reduce the speed of the circuit or increase power consumption, making the benefits of scaling down smaller and smaller . [0003] In order to optimize the reliability design of the circuit, a set of reliability analysis methods must first be established, that is, the performance of the circuit under the influence of degradation and process fluctuations should be...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/398G06F30/33G06F30/367G06F119/02
CPCG06F30/398G06F30/33G06F30/367G06F2119/02
Inventor 王润声张作栋张喆黄如
Owner PEKING UNIV
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