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A method of circuit reliability analysis

An analysis method and reliable technology, applied in CAD circuit design, electrical digital data processing, instruments, etc., can solve problems such as high complexity, low precision, difficult to support fluctuation and aging analysis, and achieve faster speed and better simulation results accurate effect

Active Publication Date: 2022-07-26
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] It can be seen that the existing circuit reliability simulation technology is difficult to support fluctuation and aging analysis, it is difficult to support statistical static timing analysis (statistical static timing analysis), and the accuracy is low and the complexity is high

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  • A method of circuit reliability analysis
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Embodiment Construction

[0024] Below in conjunction with the accompanying drawings, the present invention is further described by means of embodiments, but the scope of the present invention is not limited in any way.

[0025] The invention provides a path-based circuit reliability analysis method, which does not need to establish a standard cell library of degradation perception, and can also support statistical static timing analysis. figure 1 Shown is the process flow of the method of the present invention, and the specific implementation comprises the following steps:

[0026] Step 1. Pick a representative path:

[0027] In order to realize the path-based analysis, the present invention proposes a new representative path selection method. Although the degradation rates of different paths are different, it is impossible for a path with a small initial delay to become a critical path. First, static timing analysis is performed, and then short paths whose initial delay is less than 90% of the init...

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Abstract

The invention discloses a circuit reliability analysis method, which relates to integrated circuit reliability design technology. First, the circuit is synthesized, path analysis and workload calculation are performed, and the input condition and load condition and degradation degree of each logic gate on the critical path are obtained; Then perform transistor-level Monte Carlo simulation, use transistor-level simulation degradation information, and do not need to establish a standard cell library for circuit degradation awareness, thereby making the simulation results more accurate, accelerating the application of nodes in the circuit, and supporting statistical static timing analysis.

Description

technical field [0001] The invention relates to integrated circuit reliability design technology, in particular to a circuit reliability analysis method. Background technique [0002] As microelectronics processes continue to be scaled down, reliability issues are getting worse. Under advanced process nodes, process variation and transistor aging bring greater uncertainty to the life of the circuit, making the design margin of the circuit smaller and smaller. In order to meet the service life requirements of the circuit, it is necessary to add a larger frequency / voltage guardband in the design, which will reduce the speed of the circuit or increase the power consumption, making the benefits of scaling down smaller and smaller. . [0003] In order to optimize the reliability design of a circuit, a set of reliability analysis methods must first be established, that is, the performance of the circuit under the influence of degradation and process fluctuations should be consid...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/398G06F30/33G06F30/367G06F119/02
CPCG06F30/398G06F30/33G06F30/367G06F2119/02
Inventor 王润声张作栋张喆黄如
Owner PEKING UNIV
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