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Self aligned triple patterning

a triple patterning and self-aligning technology, applied in the field of sequence processing, can solve problems such as inability to reliably form photolithographic techniques

Inactive Publication Date: 2012-04-12
APPLIED MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0007]Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned triple patterning (SATP) process. A stack of layers is patterned near the optical resolution of a photolithography system using a high-resolution photomask. The heterogeneous stacks are selectively etched to undercut a hard mask layer beneath overlying cores. A dielectric layer, which is flowable during formation, is deposi

Problems solved by technology

Due to factors such as optics and light or radiation wavelength, however, photolithography techniques have a minimum pitch below which a particular photolithographic technique may not reliably form features.
Multiple hard mask spacers give rise to process control challenges involving matching of the multiple thicknesses and other repeated process parameters.

Method used

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Embodiment Construction

[0015]Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned triple patterning (SATP) process. A stack of layers is patterned near the optical resolution of a photolithography system using a high-resolution photomask. The heterogeneous stacks are selectively etched to undercut a hard mask layer beneath overlying cores. A dielectric layer, which is flowable during formation, is deposited and fills the undercut regions as well as the regions between the heterogeneous stacks. The dielectric layer is anisotropically etched and a conformal spacer is deposited on and between the cores. The spacer is anisotropically etched to leave two spacers between each core. The cores are stripped and the spacers are used together with the remaining hard mask features to pattern the substrate at triple the density of the original pattern.

[0016]In order to better understand and appreciate the invention, reference is made to FIG. 2, which is a flow...

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Abstract

Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned triple patterning (SATP) process. A stack of layers is patterned near the optical resolution of a photolithography system using a high-resolution photomask. The heterogeneous stacks are selectively etched to undercut a hard mask layer beneath overlying cores. A dielectric layer, which is flowable during formation, is deposited and fills the undercut regions as well as the regions between the heterogeneous stacks. The dielectric layer is anisotropically etched and a conformal spacer is deposited on and between the cores. The spacer is anisotropically etched to leave two spacers between each core. The cores are stripped and the spacers are used together with the remaining hard mask features to pattern the substrate at triple the density of the original pattern.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This application is a nonprovisional of, and claims the benefit of the filing date of U.S. Provisional Patent Application No. 61 / 390,955, filed Oct. 7, 2010, entitled “SELF ALIGNED TRIPLE PATTERNING” by Bencherki Mebarki et al., the entire disclosure of which is incorporated herein by reference for all purposes.BACKGROUND[0002]The application relates generally to substrate processing methods and particularly to process sequences which increase the density of features on the substrate.[0003]Shrinking integrated circuits (ICs) may result in improved performance, increased capacity and / or reduced cost. Each device shrink requires more sophisticated techniques to form the features. Photolithography is commonly used to pattern features on a substrate. An exemplary feature is a line of a material which may be a metal, semiconductor or insulator. Linewidth is the width of the line and the spacing is the distance between adjacent lines. Pitch is d...

Claims

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Application Information

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IPC IPC(8): C23F1/02
CPCH01L21/0338H01L21/0337
Inventor MEBARKI, BENCHERKICHEN, HAOSAPRE, KEDARWANG, ANCHUANMANDREKAR, TUSHARLIANG, JINGMEICHEN, YONGMEINGAI, CHRISTOPHER S.NAIK, MEHUL
Owner APPLIED MATERIALS INC
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