Digital signal transition counters for digital integrated circuits

Abstract

A digital integrated circuit may include a digital data processing circuit having multiple signal lines that each go through signal transitions during operation of the digital data processing circuit. A digital counter circuit may count the combined number of signal transitions that take place on at least two of the multiple signal lines during operation of the digital circuit. A digital counter circuit may count the number of times a particular pattern of signal transitions takes place on at least one signal line during operation of the circuit. A computer program may receive information indicative of a composition of a digital integrated circuit, input vectors to the digital integrated circuit, and how much power is being consumed by the digital integrated circuit under each of the input vectors. The program may output information indicative of an amount of power being consumed by each of multiple, different sub-sections of the digital integrated circuit while responding to the input vectors.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is based upon and claims priority to U.S. provisional patent application 61 / 805,452, entitled ACCURATE DIGITAL SENSORS FOR DIGITAL CIRCUITS,” filed Mar. 26, 2013, attorney docket number 028080-0882. This application is related to U.S. patent application Ser. No. 13 / 719,916, entitled “Digital Circuit Power Measurements Using Numerical Analysis,” filed Dec. 19, 2012, attorney docket number 028080-0821, which is based upon and claims priority to U.S. provisional patent application 61 / 589,988, entitled “Method of Measuring Accurate Dynamic Power Consumption of Integrated Component and Sub-Circuits,” filed Jan. 24, 2012, attorney docket number 028080-0705. The entire content of these patent applications is incorporated herein by reference.BACKGROUND[0002]1. Technical Field[0003]This disclosure relates to determining the amount of power being used by digital circuits and to power management and other applications for this infor...

AI Technical Summary

Benefits of technology

The patent describes a digital integrated circuit with a counter circuit that tracks the number of signal transitions on multiple signal lines. This helps to measure the power consumption of the circuit and identify areas that may be using too much power. The circuit also includes a non-linear compensation circuit that adjusts for changes in the number of signal transitions and power consumption. The patent also includes a computer program that allows for the analysis of the circuit's composition and the identification of specific signal lines that may be consuming too much power. Overall, the technical effect of the patent is to provide a way to measure and improve the efficiency of digital circuits.

Problems solved by technology

However, it may introduce practical challenges for emerging platforms such as mobile phones and systems-on-chips (SOCs).

These challenges may include scalability, instrumentation error, and ADC related resource overhead.

However, the system may rely on values from external ADCs over long windows of time to build workload specific power models.

With significant differences found in resulting power models across different workloads, errors can be evident, even at low sampling rates and fewer channels

However, unlike in the past, it may no longer be possible to use overly pessimistic estimates, since the overheads of corresponding overdesign are growing.

Also, such overheads are becoming much less acceptable as the gains provided by each new technology generation are diminishing for many key parameters

One of the key consequences of this is that static estimation approaches, i.e., low run-time complexity approaches that analyze a circuit without using any particular input vector sequence by implicitly capturing the worst-case over all possible sequences, are becoming less acceptable since worst-case analysis is typically pessimistic for many important parameters.

While the availability of tools that capture process variations has been growing, these may have higher run-time complexities than their classical counterparts.

The run-time complexity may be particularly high when trying to capture the impact of variations during dynamic analyses and simulations.

However, such techniques may suffer instrumentation errors, aging, scalability, and delays associated with ADCs.

Also, as the intrinsic gain of transistors decreases with manufacturing technology scaling, it may become harder to implement such technologies using on-chip ADCs.

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