Embedded package structure and method for manufacturing thereof

Abstract

The disclosure provides an embedded package structure comprising a metal substrate, a chip module, an insulation material layer, and at least one patterned metal layer. The metal substrate has a first surface and a second surface. The chip module is disposed on the first surface of the metal substrate, and comprises at least two stacked chips being electrically connected to each. The insulation material layer covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection formed therein. The patterned metal layer is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure also provides.

Description

BACKGROUND[0001]1. Technical Field[0002]The present disclosure relates to a package structure, and more particularly, to an embedded package structure.[0003]2. Description of Related Art[0004]A schematic sectional view of a conventional embedded package structure 100 is shown in FIG. 1, which is a single-chip embedded structure including chips 110, metal layers 120, an insulation material layer 130 and two passivation layers 140.[0005]As shown In FIG. 1, the chips 110, the metal layers 120 and an insulation material layer 130 are sandwiched between the passivation layers 140. The chips 110 are individually positioned in the insulation material layer 130, and electrically connected to other chips 110 through the metal layers 120.[0006]Since there are the numerous metal routing layers connecting to the chips, parasitic effects may appear in the embedded package structure to damage the chips. Besides, due to the numerous metal routing layers, the signal transmission distance in the sin...

AI Technical Summary

Benefits of technology

The present patent discusses an embedded package structure and a method for manufacturing it. The structure includes a metal substrate, a chip module, an insulation material layer, and at least one patterned metal layer. The technical effect of this patent is to provide a more efficient and compact way of integrating chip modules into electronic devices.

Problems solved by technology

Since there are the numerous metal routing layers connecting to the chips, parasitic effects may appear in the embedded package structure to damage the chips.

Besides, due to the numerous metal routing layers, the signal transmission distance in the single-chip embedded structure is so long that the intensity and quality of the signal may deteriorate.

On the other way, the conventional embedded package structure having lots of chips inside always has a large size, which is unfavorable in design of a compact device.

Images