Apparatus and Method to Switch Packets Using a Switch Fabric With Memory

Abstract

Packets having at least one cell are switched using input queues, output queues, a switch fabric, and a controller. Each input queue stores cells to be switched, and each output queue stores switched cells. The switch fabric couples the input queues to the output queues and has memory. The switch fabric stores cells moved from the input queues to the switch fabric and stores cells based on the output queues. The controller couples to the input queues and the switch fabric and determines input priorities for cells moving from the input queues to the switch fabric and output priorities for cells moving from the switch fabric to the output queues.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of U.S. application Ser. No. 10 / 606,753, filed on Jun. 27, 2003, now U.S. Pat. No. 8,937,964, which claims the benefit of U.S. Provisional Application No. 60 / 392,422, filed on Jun. 27, 2002. The entire teachings of the above applications are incorporated herein by reference.TECHNICAL FIELD OF THE INVENTION[0002]The present invention relates in general to communications networks and more particularly to apparatuses and methods for scheduling packets in packet switching devices.BACKGROUND OF THE INVENTION[0003]For the convenience of the reader, the publications referred to herein are listed below. As used herein, the numerals within parentheses refer to the respective publications. The listed publications are incorporated herein by reference.[0004](1) D. Stephens and H. Zhang, “Implementing Distributed Packet Fair Queueing in a Scalable Switch Architecture,” Proc. IEEE INFOCOM 1998, pp. 282-290, April 1998...

AI Technical Summary

Benefits of technology

This approach enables a less expensive switch design that achieves substantially the same performance as an OQ switch, with improved throughput and delay guarantees, using a CIFOQ architecture with input and output line card buffering and flow-control.

Problems solved by technology

However, the OQ switch architecture can be rather expensive to build for devices with fast line rates or with many input and output ports.

Unfortunately, OQ switches are expensive to build for large Nor for high-speed data lines.

The high cost results from the fact that the memory associated with each output port must store up to N newly arrived packets and retrieve one outgoing packet in a packet time.

The performance, however, can often fall far short of the OQ switch.

For example, various industry approaches for the CIFOQ architecture have throughput and delay guarantee limitations (see (1)-(3)).

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