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Method for manufacturing three dimensional stacked semiconductor structure and structure manufactured by the same

a three-dimensional stacked semiconductor and manufacturing method technology, applied in the direction of semiconductor devices, basic electric elements, electrical apparatus, etc., can solve the problems of easy bended or collapsed problems, and the typical 3d memory structure suffers from several problems, and achieves reliable electrical characteristics.

Active Publication Date: 2015-11-19
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patent is about a new method of making a 3D semiconductor structure. This method solves problems with previous methods, which often resulted in bending or col(1)ling of the structure during manufacturing. The new method involves, among other things, a multi-layer arrangement with alternating layers that compress and expand. This arrangement is important to provide the strength and stability needed for a reliable electrical profile. The overall effect is a strengthened and self-aligned profile that improves the manufacturing process for 3D semiconductor structures.

Problems solved by technology

However, the typical 3D memory structure suffers from several problems.
For the conventional 3D stacked semiconductor structure and manufacturing method, the easily bended or collapsed problems occurred often due to higher aspect ratio. FIG. 1 schematically shows the bended pillars occurred in the conventional 3D stacked semiconductor structure.
If the pillars of the 3D stacked semiconductor structure are tall and narrow, it is easily bended or collapsed.
Also, the multi-layered pillars of the 3D stacked semiconductor structure are oxide-and-polysilicon (O-P) stacks, which exhibit unbalanced stress, and are easily collapsed or bended during manufacturing processes.

Method used

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  • Method for manufacturing three dimensional stacked semiconductor structure and structure manufactured by the same
  • Method for manufacturing three dimensional stacked semiconductor structure and structure manufactured by the same
  • Method for manufacturing three dimensional stacked semiconductor structure and structure manufactured by the same

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Embodiment Construction

[0020]In the embodiments of the present disclosure, a method of manufacturing a three-dimensional (3D) stacked semiconductor structure and a structure manufactured by the same are provided. According to the method of the embodiment, a multi-layer comprising a plurality of first and second dielectric layers arranged alternately are formed on a substrate, followed by patterning the multi-layer to form a plurality of first patterned stacks and spaces between the first patterned stacks. According to the embodiment, the first dielectric layers are compressive layers exhibiting compressive stress, and the second dielectric layers are tensile layers exhibiting tensile stress. Parts of the second dielectric layers of one of the first patterned stacks are then replaced by conductors. The 3D stacked semiconductor structure manufactured by the method of the embodiment has plural multi-layered patterned stacks and spaces between the multi-layered patterned stacks, and each patterned stack compr...

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Abstract

A method of manufacturing a three-dimensional (3D) stacked semiconductor structure is provided, comprising. A multi-layer on a substrate is formed, and the multi-layer comprises plural first dielectric layers and second dielectric layers arranged alternately. The multi-layer is then patterned to form plural first patterned stacks and spaces between the first patterned stacks, wherein one of the first patterned stacks has a width of FO while the one of the spaces has a width of Fs. In one embodiment, FO is equal to or more than 2 times Fs. Parts of the second dielectric layers of one of the first patterned stacks are removed, so as to form plural first cavities in the first patterned stack. Then, the first cavities in the first patterned stack are filled with conductors.

Description

BACKGROUND[0001]1. Field of the Invention[0002]The disclosure relates in general to a method of manufacturing a three-dimensional (3D) stacked semiconductor structure and a structure manufactured by the same, and more particularly to the method for manufacturing the structure having dielectric supports for multi-layered pillars, thereby strengthening the overall construction.[0003]2. Description of the Related Art[0004]A nonvolatile semiconductor memory device is typically designed to securely hold data even when power is lost or removed from the memory device. Various types of nonvolatile memory devices have been proposed in the related art. Also, manufactures have been looking for new developments or techniques combination for stacking multiple planes of memory cells, so as to achieve greater storage capacity. For example, several types of multi-layer stackable NAND-type flash memory structures have been proposed. However, the typical 3D memory structure suffers from several probl...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/115
CPCH01L27/11582H01L27/10844H01L27/11578H10B43/27H10B43/20H10B12/01
Inventor LAI, ERH-KUN
Owner MACRONIX INT CO LTD
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