Metal gate structure

Abstract

The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This patent application is a continuation application of and claims priority to U.S. patent application Ser. No. 14 / 463,677, filed on Aug. 20, 2014, and entitled “Method of fabricating metal gate structure” the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates generally to the field of semiconductor devices, and more particularly to metal gate structures having gate trenches with different widths.[0004]2. Description of the Prior Art[0005]With the trend of miniaturization in the semiconductor industry with corresponding improvements in semiconductor manufacturing processes, manufactures are able to form both dense regions and sparse regions on one chip.[0006]During an etching process of fabricating patterned structures, however, etching rates in the dense regions are often different from those in the sparse regions due to density diff...

AI Technical Summary

Benefits of technology

[0007]A metal gate structure and a method for fabricating the same are therefore disclosed according to embodiments of the present invention.

Problems solved by technology

During an etching process of fabricating patterned structures, however, etching rates in the dense regions are often different from those in the sparse regions due to density difference.

For example, the trenches in the sparse regions are usually deeper than those in the dense regions, which may cause a pre-layer to be exposed from the bottom of the trenches and negatively affect the electrical propertied of the corresponding semiconductor devices.

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