Memory device and associated erase method

Abstract

A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.

Description

FIELD OF THE INVENTION[0001]The present invention relates to a memory device and an erase method thereof, and more particularly to a memory device in a pipeline configuration and an erase method thereof.BACKGROUND OF THE INVENTION[0002]A flash memory is one of the widely used non-volatile memories. Generally, a flash memory chip includes plural memory cells.[0003]FIG. 1 is a schematic cross-sectional view illustrating a memory cell of a conventional non-volatile memory. Generally, charges may be stored in the region between a control gate C and a substrate 13. The operations of the flash memory include a write operation, a read operation and an erase operation. While the write operation or the erase operation is performed, the amount of the charges stored in the region between the control gate C and a substrate 13 may be subjected to a change.[0004]Generally, a threshold voltage (Vth) of the transistor is determined according to the amount of the stored charges. During the write ope...

AI Technical Summary

Benefits of technology

This approach significantly shortens the erase time for each block, enhances overall erase speed, and reduces the likelihood of misjudging the device as malfunctioned, while maintaining storage capacity through over-provisioning buffering.

Problems solved by technology

The erase operation for erasing the block of the flash memory is lengthy and consumes a great deal of electric power.

Since the erase time period Terase is longer, the performance of the flash memory is gradually deteriorated.

Moreover, the flash memory may be erroneously judged as a malfunctioned flash memory by a control chip.

If the message about the verifying result is not successfully received by the control chip after the erase command has been issued for a predetermined time period, the control chip will consider the erase command as ineffective.

Under this circumstance, the possibility of erroneously judging the flash memory as the malfunctioned flash memory by the control chip will increase.

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