Self-aligned shallow trench isolation and doping for vertical fin transistors

Abstract

A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

Description

BACKGROUNDTechnical Field[0001]The present invention generally relates to self-aligned shallow trench isolation regions and masking of doped substrate regions, and more particularly to an approach to control the alignment of mask layers with semiconductor device features to reduce dimensional variations.Description of the Related Art[0002]A Field Effect Transistor (FET) typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the channel. Field Effect Transistors (FETs) can have a variety of different structures, for example, FETs have been fabricated with the source, channel, and drain formed in the substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate), and finFETs have been formed with the channel extending outward from the substrate, but where the current also flows horizontally from a source to a drain. The channel for the finFET can be an...

AI Technical Summary

Benefits of technology

This approach enables precise control over feature placement and inter-feature pitch, reducing dimensional variations and ensuring accurate formation of vertical finFETs with self-aligned shallow trench isolation regions, thereby overcoming scaling issues in smaller device components.

Problems solved by technology

With ever decreasing device dimensions, forming the individual components and electrical contacts become more difficult.

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