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Methods, apparatus, and system for fabricating finfet devices with increased breakdown voltage

a technology of breakdown voltage and finfet, which is applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of reducing the channel length of a fet, reducing the distance between the source region and the drain region, and affecting the electrical potential of the channel

Active Publication Date: 2018-12-13
GLOBALFOUNDRIES U S INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a method to make a fin field effect transistor (finFET) using a process called "connector formation." A first gate structure is made on a semiconductor wafer, a trench is formed adjacent to the first gate structure, and a connector is formed in the trench. The connector is made up of a thin film oxide, a liner, and a layer of tungsten. This process helps to improve the performance and reliability of the finFET. A semiconductor device processing system is also described that makes use of this method.

Problems solved by technology

However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region.
In some cases, this decreased separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain.
However, when the transistor is switched on, the shape of the channel may limit the current flow.
Those skilled in the art will appreciate that a significant number of interconnections must be made between, and to, the components of the finFETs such that routing of the interconnections may be complicated and densely packed.
Exceeding the breakdown voltage may lead to erroneous operation of the finFET device 100.

Method used

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  • Methods, apparatus, and system for fabricating finfet devices with increased breakdown voltage
  • Methods, apparatus, and system for fabricating finfet devices with increased breakdown voltage
  • Methods, apparatus, and system for fabricating finfet devices with increased breakdown voltage

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Embodiment Construction

[0029]Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0030]The present subject matter will now be described with reference to the attached Figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details ...

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Abstract

At least one method, apparatus and system is disclosed herein for forming a fin field effect transistor (finFET) device having a reduced breakdown voltage. The method comprises forming a first gate structure on a substrate of a semiconductor wafer in a first layer, the gate structure extending to a height of about h above the substrate. A trench is formed in the first layer adjacent the first gate structure and extends from a height of about d to the substrate. A connector is formed in the trench between the substrate and a layer of the finFET above the first layer. The process of forming the connector comprises; forming a thin film oxide on the sidewalls of the trench extending from a height below h to about d; forming a liner in the trench, extending over the substrate and on the sidewalls to about the height d over the thin film oxide and forming a layer of tungsten in the trench over the liner.

Description

BACKGROUND OF THE INVENTIONField of the Invention[0001]Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and more specifically, to various methods for fabricating finFET devices having increased breakdown voltages.Description of the Related Art[0002]The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/8234H01L27/088H01L29/49H01L23/535H01L23/532
CPCH01L21/823468H01L21/823431H01L21/823475H01L23/53266H01L29/4983H01L23/535H01L27/0886H01L23/485H01L29/66795H01L29/41791H01L21/76897H01L21/76831
Inventor WANG, YANZHENDOU, XINYUANGU, SIPENG
Owner GLOBALFOUNDRIES U S INC
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