Method of forming field effect transistor (FET) circuits, and forming integrated circuit (IC) chips with the fet circuits

Abstract

A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source / drain contacts are etched through the insulation and said gate dielectric layer to source / drain regions. A combination fluoroether / hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source / drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.

Description

BACKGROUND OF THE INVENTIONField of the Invention[0001]The present invention generally relates to Integrated Circuit (IC) manufacture and more particularly to manufacturing integrated circuits with self-aligned contacts to Field Effect Transistor (FET) source / drain regions.Background Description[0002]Primary integrated circuit (IC) chip manufacturing goals include increasing chip density and performance at minimized power consumption, i.e., packing more function operating at higher speeds in the same or smaller space. Transistors or devices are formed by stacking layers of shapes on the IC, e.g., printed layer by layer on a wafer using photolithographic techniques. A simple field effect transistor (FET), or device, includes a gate above a semiconductor channel, a dielectric gate sidewall spacer, e.g., nitride, over source / drain extensions at each end of the channel, and source / drain regions outboard of the gate sidewall spacers. In arrays, for example, two or more devices share sour...

AI Technical Summary

Problems solved by technology

However, as device features shrink, sidewall spacers have to shrink too, and unfortunately, previously negligible effect are becoming problematic.

Chemical effects of the etchants tend to thin the sidewall spacers even further.

Thinner sidewall spacers result in source / drain extensions that are shorter than intended, changing device characteristics and further exposing the gate to shorts.

Consequently, these unintended physical and chemical effects can dramatically lower yield.

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