Signal processing apparatus and method, program, and storage medium

a signal processing and signal processing technology, applied in the field of signal processing apparatus and method, a program, and a storage medium, can solve the problems of long conversion process and difficulty in implementing the discrete wavelet transformation of an imag

Active Publication Date: 2006-04-18
CANON KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0046]a first wavelet transformation step of applying a wavelet transforms to the two-dimensional signals...

Problems solved by technology

Conventionally, it is difficult to implement the discrete wavelet transformation of an image due to its memory cost problems, complexity in calculations, and the like.
However, in this case, assume that such signal extension processes are ...

Method used

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  • Signal processing apparatus and method, program, and storage medium
  • Signal processing apparatus and method, program, and storage medium
  • Signal processing apparatus and method, program, and storage medium

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first embodiment

[0068]FIG. 1 is a block diagram showing the basic arrangement of a signal processing apparatus of this embodiment. Referring to FIG. 1, reference numeral 100 denotes a signal input unit; 101, a signal storage processor; 102, a buffer; 103, a vertical discrete wavelet transformer; 105 and 106, horizontal discrete wavelet transformers; and 107 and 108, signal lines.

[0069]Assume that the signal processing apparatus of this embodiment computes the transforms of 2D signals which have X samples in the horizontal direction, and Y samples in the horizontal direction, and in which each sample is expressed by 8 bits, as in the conventional method described above. Also, Sx represents the number of samples in the horizontal direction of signals input to the apparatus of this embodiment. The buffer 102 stores signals and intermediate values of arithmetic operations for a plurality of lines, which are required to implement a 5×3 filter. As described above, upon implementation without lifting, sig...

second embodiment

[0079]FIG. 7 is a block diagram showing the basic arrangement of a signal processing apparatus of this embodiment. Referring to FIG. 7, reference numeral 800 denotes a signal input unit; 801, a signal storage processor; 802, a buffer; 803, a vertical discrete wavelet transformer; 805 and 806, horizontal discrete wavelet transformers; and 807 and 808, signal lines. This block diagram is the same as the basic arrangement of the signal processing apparatus in the first embodiment (shown in FIG. 1), but processes executed by the respective units in the signal processing apparatus of this embodiment are different from those executed by the respective units in the signal processing apparatus of the first embodiment. The processes in the respective units in the signal processing apparatus of this embodiment will be explained below.

[0080]Assume that the signal processing apparatus of this embodiment computes the transforms of 2D signals which have X samples in the horizontal direction, and ...

third embodiment

[0092]FIG. 10 is a block diagram showing the basic arrangement of a signal processing apparatus of this embodiment. Referring to FIG. 10, reference numeral 800 denotes a signal input unit; 801, a signal storage processor; 1001, a vertical discrete wavelet transformer; 1002, a horizontal discrete wavelet transformer; and 1003 and 1004, signal lines. The same reference numerals in the third embodiment denote blocks which execute the same operations as in the second embodiment. The first and second embodiments comprise two horizontal discrete wavelet transformers, which respectively compute the discrete wavelet transforms of the coefficients of low- and high-frequency components output from the vertical discrete wavelet transformer in the horizontal direction. However, in the arrangement of this embodiment, only one horizontal discrete wavelet transformer is used.

[0093]The operation of the respective units of this embodiment will be described below using FIG. 10.

[0094]Assume that the s...

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PUM

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Abstract

A signal storage processor (101) stores signals input from a signal input unit (100) in a buffer (102) for respective lines. A vertical discrete wavelet transformer (103) reads out an index value L from the signal storage processor (101), and obtains a reference address B from the value L. If L=2, B=2. If L=4, B=0. Furthermore, the vertical discrete wavelet transformer (103) reads out the i-th column of sets of data, which are stored in the buffer (102) and are continuous in the vertical direction (i.e., data read out from four addresses (addresses in the buffer (102)) i×4+B, i×4+mod((B+1),4), i×4+mod((B+2),4), and i×4+mod((B+3),4)), and computes the one-dimensional discrete wavelet transforms of the readout data.

Description

FIELD OF THE INVENTION[0001]The present invention relates to a signal processing apparatus and method, a program, and a storage medium.BACKGROUND OF THE INVENTION[0002]In recent years, discrete wavelet transformation has received a lot of attention in various fields of image processes such as analysis, compression, and recognition of digital signals. Especially, in the image compression field, since a signal entropy reduction effect of the discrete wavelet transformation is high, and a subband decomposition process is suitable for scalable transmission of an image, image compression methods using the discrete wavelet transformation have been extensively examined. It is already determined that a new still image encoding scheme JPEG2000, which will be recommended soon as international standards ITU-T T.800|ISO / IEC 15444, would adopt discrete wavelet transformation.[0003]Conventionally, it is difficult to implement the discrete wavelet transformation of an image due to its memory cost ...

Claims

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Application Information

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IPC IPC(8): G06K9/46G06F17/14G06T9/00H03M7/30H04N1/41H04N19/33H04N19/423H04N19/60H04N19/63H04N19/80
CPCG06T9/007
Inventor KAJIWARA, HIROSHI
Owner CANON KK
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