Method and apparatus for generating minimal node data and dynamic assertions for a simulation

Abstract

A system for tracing a simulation design involves an encoded assertion asserting a value of a node of the simulation design at a point in a simulation, a fanin cone detection facility configured to obtain a fanin cone for the encoded assertion, a waveform trace facility configured to obtain waveform data including a history of signal values for the node, and a simulation toolkit configured to obtain node data using the fanin cone and the waveform data.

Description

BACKGROUND OF INVENTION[0001]Modern high performance electronic circuitry has an ever-increasing number of circuit elements and an ever-rising clock frequency. As circuitry performance continues to increase, the result has been a larger number of circuits switching at faster rates. After a circuit prototype is initially manufactured and failure modes are uncovered, determining failure mechanisms is time intensive due to the increased circuit complexity. Circuit failures may be the result of logic errors or poor manufacturability of a circuit element. In both cases, simulation of the circuit helps to confirm or refute the existence of a logic error and verify the correctness of the design.[0002]Simulation may occur at low levels of abstraction, e.g., at a “switch-level.” Switch-level simulations typically include active circuit elements (e.g., transistors) and passive circuit elements (e.g., resistors, capacitors, and inductors). CPU simulation also may occur at a higher level of abs...

AI Technical Summary

Problems solved by technology

After a circuit prototype is initially manufactured and failure modes are uncovered, determining failure mechanisms is time intensive due to the increased circuit complexity.

Circuit failures may be the result of logic errors or poor manufacturability of a circuit element.

For example, the designer may determine that a particular gate associated with a node in the fanin cone is faulty, which caused an unexpected signal value, resulting in the failed assertion.

In other cases, the designer may not be able to determine the cause of the failed assertion.

For example, the node data obtained by the designer may be incorrect.

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