Learning based logic diagnosis

Abstract

A system and method for diagnosing a failure in an electronic device. A disclosed system comprises: a defect table that associates previously studied features with known failures; and a fault isolation system that compares an inputted set of suspected faulty device features with the previously studied features listed in the defect table in order to identify causes of the failure.

Description

BACKGROUND OF INVENTION[0001]1. Technical Field[0002]The present invention relates generally to identifying defects in a semiconductor device, and more specifically relates to a logic diagnosis system and method that utilizes a table of manufacturing characterization data to isolate and identify design features known to be error prone.[0003]2. Related Art[0004]Given the complexities involved in manufacturing a semiconductor device, it is not uncommon for a device to have numerous operational faults in the early production stages. Identifying and analyzing these faults remains an important and costly challenge.[0005]Traditional logic diagnosis relies on fault simulation software, which determines a set of logic nets (i.e., circuits) that are suspected to be at fault. Fault simulation software examines the logic of the faulty device, as well as logs of input and output values obtained from operating the actual device, and generates a list of suspect nets that might be causing the defe...

AI Technical Summary

Benefits of technology

The present invention provides a system, method, and program product for diagnosing failures in electronic devices. It uses a defect table that associates previously studied features with known failures to identify the causes of the failure. The system can simulate the operation of the device, determine potential features that may cause the failure, and compare them with the previously studied features in the defect table to identify the cause. This helps to quickly and accurately diagnose failures in electronic devices.

Problems solved by technology

Given the complexities involved in manufacturing a semiconductor device, it is not uncommon for a device to have numerous operational faults in the early production stages.

Identifying and analyzing these faults remains an important and costly challenge.

From the suspect set of nets, a costly physical analysis is then implemented to attempt to link the defect to a particular physical location and / or manufacturing step.

Unfortunately, the suspected set of nets often span across a large portion and various levels of the physical chip layout, thereby driving up the costs of the necessary physical analysis.

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